Can I insert wait states during the transmission of Transaction Layer Packets (TLPs)? For example, there is an input to the transaction interface called trn_tsrc_rdy_n. Can this signal be used to insert wait states during the transmission of TLPs?
You can pause the transfer of packets between the user application and the PCI Express Core by deasserting trn_tsrc_rdy_n. There is no limit to the number of cycles that trn_tsrc_rdy_n can be deasserted. The PCI Express Core holds the packet in its transmit buffer until you finish moving the packet into the core signified by the assertion of trn_teof_n. Once the complete packet is stored inside the core, it is transmitted on the PCI Express Link. You cannot directly affect the packet's transmission on the link through trn_tsrc_rdy_n. However, if you deassert trn_tsrc_rdy_n excessively it slows the overall bandwidth because the core does not have the packet to send until you assert trn_teof_n.
NOTE: Currently, you must pause back-to-back TLPs by at least one cycle by deasserting trn_tsrc_rdy_n. Please see (Xilinx Answer 21708) for more information.