We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21717

Spartan-3E, IDDR2 - Cascaded data path is not programmed correctly in some instances


When using the IDDR2 component and setting the DDR_ALIGNMENT attribute to either "C1" or "C0", the design does not work in hardware. The timing simulation indicates that the design should work.


The cascaded data path used when DDR_ALIGNMENT is set to either "C0" or "C1" is not programmed correctly in hardware, which means that the input data is not registered correctly.

This problem has been fixed in the latest 7.1i Service Pack available at:

The first service pack containing the fix is 7.1i Service Pack 4.

IDDR2 can still be used correctly when DDR_ALIGNMENT is set to "NONE", which is the default setting.

AR# 21717
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked