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AR# 21723

11.5 PAR - "WARNING:Route:455 - CLK Net:trn_clk_OBUF may have excessive skew..."


My design was successfully implemented in ISE software, and all my timing requirements were met. However, in the Place and Route report, I see the following warning for some clock nets in my design:
"WARNING:Route:455 - CLK Net:trn_clk_OBUF may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template."
Can I ignore this warning?


This message informs the user that some loads on the clock net are not clock pins. Therefore, the clock template that is normally used to connect clock pins will not be used to connect the loads. A different routing that involves local routing will be used, potentially inducing some skew on the clock net.
Opening your design in FPGA EDITOR will allow you to see what loads are connected to the clock net, and the cause of the warnings.
The amount of skew on the net will be reported in the Place and Route report.
If the loads on the net shown in FPGA Editor are in accord with your design, the skew reported in the PAR report is not critical for the design, and the timing constraint requirement on that net is met, then this warning can be safely ignored.
AR# 21723
Date 12/15/2012
Status Active
Type General Article
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