During configuration, I notice that CCLK stays High for what appears to be a number of clock cycles. Why?
When CCLK changes from the default frequency to the configuration frequency defined by you, the FPGA must execute a synchronous clock switch. During this switch, the CCLK signal stays High while the multiplexer switches between locations on an internal clock divider. This prevents the CCLK from glitching and double-clocking data; however, it appears as if two to three CCLK cycles are missing.
Since this CCLK switching only occurs in master mode when the FPGA is providing the configuration clock, there is no detrimental effect on the application.