Urgency : Standard
When I create a model in System Generator 7.1, the model simulates correctly but when the .bit file is downloaded to the device or hardware co-simulation is performed, the design does not work i.e. no outputs are seen. The same design will function in hardware when using System Generator 6.3
There is an issue in System Generator 7.1, whereby the ce_clr port is brought out at the toplevel of the design. This port is usually optimized away by the tools. The ce_clr port must be held at logic level low for the design to function. To check if this is the problem look in the design_name_clk_wrapper.pad file in your ..netlist/xflow directory, if ce_clr appears as a port then make the following changes to get your design working again.
In your design_name_clk_wrapper.vhd file change the line;
ce_clr_sysgen <= ce_clr;
ce_clr_sysgen <= '0';
The ce_clr port should now be optimized away correctly by the tools.
To make the changes you can either;
1. Generate the HDL netlist, open the project in ISE, make the change in the design_name_clk_wrapper.vhd file and then generate the bitstream in ISE.
2. Generate the HDL netlist, open the design_name_clk_wrapper.vhd file and make the changes. Then in Sysgen, change compilation type to bitstream and in the settings select Specify Alternate Clock Wrapper and point to the new changed design_name_clk_wrapper file.
This issue will be fixed in System Generator 8.1