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AR# 21817

7.1i IP Update 2 CORE Generator - IP-DSP What's New and Known Issues List

Description

Keywords: ISE, Binary Counter, Comparator, Complex Multiplier, Distributed Arithmetic FIR Filter, DVB S2 FEC Encoder, FFT, Floating-point, MAC, MACC, Pipelined Divider, RAM-based Shift Register, TCC Encoder 3GPP, LogiCORE

This Answer Record contains the IP-DSP "What's New and Known Issues" addressed in the 7.1i IP Update 2.

Solution

1

WHAT'S NEW in 7.1i IP UPDATE 1

Binary Counter v8.0 r1
New Features in v8.0 r:
- Support added for Virtex-4
- Support added for ISE 7.1i
- Area and speed improvements
- Error checking for illegal values and combinations of parameters extended to include error checking in behavioral models
- New addsub used to optimize bypass and constant count cases

Bug Fixes in v8.0 r1:
- Maximum output width reduced to 30 bits
- CR 207668: Core does not generate when data is entered in hex format, and a step size of greater than 10 is specified
- Miscellaneous GUI fixes

Floating Point Cores v1.0 r1
Features in v1.0 r1:
- First release
- IEEE-754 compliant floating-point operators with only minor documented deviations
- Can be configured for high-speed operation with an instruction issued on every clock cycle
- Supports add/subtract, multiply, divide and square-root operations, with a range of standard and nonstandard sizes, including single and double precision
- Support for Virtex-4 DSP48 feature
- Includes multi-cycle divide and compare operations for single precision
- VHDL behavioral model
- Core can be generated directly from a VHDL instantiation with XST transparently calling CORE Generator

Bug Fixes in V1.0 r1:
- CR209982: Data sheet modified to explain how a Verilog simulation model can be generated for the core

Reed Solomon Encoder v5.0 r1
New Features in v5.0 r1:
- Support added for Virtex-4
- Support added for variable number of check symbols
- Support added for implementation architectures for the check symbol generator
- Support added for generating a Verilog simulation model using the "Structural" option

Bug Fixes in v5.0 r1:
- To generate a Verilog simulation model, select the "Structural" Box from the "Generation" Tab on the "Project -> Project Options" menu

2

KNOWN ISSUES in 7.1i IP UPDATE 1

LogiCORE Binary Counter v8.0
- Mismatch between behavioral and timing simulation on the THRES0 output. See (Xilinx Answer 21411).
- Mismatch between behavioral and timing simulation on the Q output. See (Xilinx Answer 21412).
- Binary Counter does not generate when I enter the data in Hex and step size of greater than 10. See (Xilinx Answer 21413).
- Binary Counter does not have a Verilog Simulation Model. See (Xilinx Answer 21983).

LogiCORE Complex Multiplier v2.1
- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).

LogiCORE Distributed Arithmetic FIR Filter (DA FIR) v9.0
- CORE Generator memory consumption issues occur with the DA FIR. See (Xilinx Answer 18663).
- Half-band output width behavioral model does not match the netlist output width. See (Xilinx Answer 21414).
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).
- Interpolating half-band fails to check for zeros in coefficients. See (Xilinx Answer 20840).

LogiCORE Fast Fourier Transform (xFFT) v3.1
- Virtex-4 speed numbers in the data sheet are incorrect. See (Xilinx Answer 21453).

LogiCORE MAC v4.0
- Virtex-4 max number of cycles. See (Xilinx Answer 21511).

LogiCORE Pipelined Divider v3.0
- How to perform a Verilog Behavioral Simulation. See (Xilinx Answer 20615).

LogiCORE RAM-based Shift Register v8.0
- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).

3

KNOWN ISSUES in Existing IP

LogiCORE CIC v3.0
- The CIC v3.0 filter exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).

LogiCORE CORDIC v3.0
- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).

LogiCORE DA FIR Filter, MAC FIR
- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).

LogiCORE DDC v1.0, MAC FIR v5.0
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE DCT v2.1
- DCT can be implemented in the Spartan-3 and Virtex-4 devices. See (Xilinx Answer 18937).

LogiCORE DCT v2.1
- DCT output width is incorrectly calculated, causing Java errors. See (Xilinx Answer 20459).

LogiCORE DDS v5.0
- DDS Data Sheet has an obsolete web link. See (Xilinx Answer 21397).

LogiCORE DDS v5.0
- DDS channel output does not operate as expected. See (Xilinx Answer 21474).

LogiCORE 1024-pt FFTv1.0
- The block RAM configurations in the FFT/IFFT Data Sheet do not match the hardware configurations. See (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0
- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0
- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0
- No Verilog model is available for the FFT Core. See (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0
- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).

LogiCORE FFT
- Simulation of all fixed netlist FFT (64, 256, 1024) cores generates many warnings. See (Xilinx Answer 14861).
- Information on output connections to the fixed netlist FFT (64, 256, 1024) cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).

LogiCORE MAC FIR v5.1
- Information on support for multiple MAC FIRs with different COE files in the same project. See (Xilinx Answer 16433).
- Back-annotated Verilog simulation causes memory collision errors. See (Xilinx Answer 16106).


LogiCORE Reed Solomon v5.0
- Information on the Ghost Enable pin in the GUI. See (Xilinx Answer 19526).
- Processing delay warning for 2 Channel Reed Solomon. See (Xilinx Answer 21769).

LogiCORE 3GPP Turbo Convolutional Decoder (TCC Decoder 3GPP) v1.0
- SDF constructs error in timing (post-PAR) simulation, when using ModelSim. See (Xilinx Answer 21434).
AR# 21817
Date Created 09/04/2007
Last Updated 03/30/2009
Status Archive
Type General Article