This Answer Record contains Release Notes and Installation information for LogiCORE PCI Express PIPE Core v1.2 Release.
The PCI Express PIPE Core is now available through CORE Generator and is no longer available for direct download from the PCI Express Lounge.
Please note that the PCI Express Endpoint Core targeting Virtex-4 is still available only through the PCI Express Lounge,
The following is a listing of Release Notes and Known Issue links for LogiCORE PIPE Version 1.2
Users familiar with v1.1 of the PCI Express PIPE Core will notice the following changes with the new CORE Generator v1.2 PIPE Core:
- Removed cfg_cfg configuration bus port. The core is now customized using the CORE Generator IP customization GUI.
- Added fast_train_simulation_only input port. Reduces training values in order to accelerate core initialization for simulation. This input should be driven to a "1" for simulation but "0" for hardware operation. For an example on how this can be done, see the "Xilinx_pci_exp_1_lane_epipe_ep.v" file found in the "example_design" directory.
- Added two_plm_auto_config input port that forces core to act as a downstream device for link training purposes, enabling the simulation of two linked cores. This bit should be set to "1" only if in simulation you are connecting two Xilinx cores together. For normal system operation where the PIPE Core will be interfacing with another device, this bit should be set to a "0." For an example on how this can be done, see the "Xilinx_pci_exp_1_lane_epipe_ep.v" file found in the "example_design" directory.
- Obsoleted sys_clk. "sys_clk" is no longer used and should be left disconnected.
- CORE Generator project must be set to target a Spartan-3 for the core to appear.
-Refer to the NXP data sheet for PX1011B errata items. PX1011B errata items are included in section 14 of the data sheet.
This data sheet is available at:
NXP Product Page:
-Users must download a patch for XST. During the PIPE core generation, it must pass parameters to XST for synthesis. For this to work properly, users must install the patch listed in (Xilinx Answer 22104) before generating a PIPE core in CORE Generator.
-Users must download the tactical patch described in (Xilinx Answer 22233). This patch fixes a problem with setting the correct maximum payload size value in the PIPE core customization GUI in CORE Generator. This patch should be installed after the PIPE core release is installed.
-CORE Generator might take up to 25 to 30 minutes to generate the core; this is expected, and times will vary depending on the speed of the individual machine.
-Users should review the "readme_pci_express_pipe.txt" file once the core is generated. This file contains important information about the release, including information about obtaining the simulation model of the Philips PX1011A-EL1 PCI Express PHY.
To obtain a license to generate the PCI Express PIPE Core, please visit the PCI Express PIPE Core lounge found at:
You will have to register and obtain a password to enter the lounge. Licenses to generate the full version of the core are available only to customers who have purchased the core.
Customers can evaluate the PIPE core without obtaining a license. Evaluation will allow simulation and implementation, but does not allow the creation of a bitstream. Once installed, you can evaluate the PIPE core using the same steps as you would to generate the actual core. A pop-up box informs users that they do not have a full license and that the core is being evaluated. For more information about evaluating the core, see:
1. ISE 7.1i with Service Pack 4 (7.1i.04i)
ISE 7.1i Service Packs can be downloaded from:
2. IP Update #3
ISE 7.1i IP Update 3 can be downloaded from:
3. Acrobat Reader Requirement
Acrobat Reader Version 5 or later must be installed to view core data sheets. You can download the latest Acrobat software from the Adobe site:
NOTE: LogiCORE PCI Express PIPE v1.2 is not available via the Automated Update using the CORE Generator Updates Installer at this time.
Supported Operating Systems are listed in the 7.1i IP Update #3 CORE Generator Release Notes. See (Xilinx Answer 21938).
1. Close the CORE Generator application if it is running.
2. Download the ".zip" file from the Xilinx Download Center, and save it to a temporary directory:
3. Extract the ".zip" file (pcie_pipe_v1_2.zip) archive to the root directory of your Xilinx software installation. Allow your extractor utility to overwrite all existing files and maintain the directory structure predefined in the archive.
4. Follow the installation instructions contained in your Xilinx Core License Request e-mail. Extract the ".zip" file (core_licenses_full.zip) that you received to the root directory of your Xilinx software installation.
Unzip the ".zip" file using WinZip 7.0 SR-1 or later.
The Xilinx software installation directory is typically located at "C:\Xilinx," if the installation defaults were used. You can verify the location of the Xilinx install by entering the following on the DOS command line:
Use UnZip to unpack the ".zip" file.
Xilinx recommends that you download the ".zip" file and unpack it using the UNIX command line unzip utility included with Xilinx software. WinZip and GNU tar are not recommended for extracting the "zip" archive because of differences in the way they handle files with long path names. See (Xilinx Answer 11162) for more details.
If you have already installed your Xilinx ISE design tools, the Xilinx installation directory location is the value of the Xilinx variable, (defined by your setup script). After sourcing your Xilinx setup script, enter the following to determine the location of your Xilinx installation:
You might need system administrator privileges to install the update.
5. Restart CORE Generator. During start-up, CORE Generator automatically detects that a new IP has been added to your installation.
6. Determine whether the installation was successful by verifying that the new core is visible in the CORE Generator GUI under the "Standard Bus Interfaces." NOTE: For this core to display, the target device must be a Spartan-3.
09/22/2009 - Added reference to NXP data sheet.