This Release Note is for the FIFO Generator 2.2 Core released in 7.1i IP Update 3, and contains the following:
- New Features
- Bug Fixes
- Known Issues
For the installation instructions and design tool requirements for 7.1i IP Update 3, see (Xilinx Answer 21938).
New Features in v2.2
Support added for using Built-in FIFO flags when constructing a FIFO from Virtex-4 built-in FIFO primitives.
Improved GUI to make "FWFT" feature more visible.
Bug Fixes in v2.2
- Modified use of the term "latency" to improve accuracy, consistency, and readability
- Modified documents to accommodate GUI change on FWFT feature which used to be called "Registered Outputs" option
Known Issues in v2.2
- In addition to the data sheet, the User Guide is available for the FIFO Generator. To access the User Guide, generate the FIFO Generator v2.2 Core and search for "fifo_generator_ug175.pdf" in your COREGen project directory.
- When using Virtex-4 FIFO16 type, the behavioral model might not show true latency on the outputs. In this case, it is strongly recommended that you use Structural simulation model. Refer to User Guide chapter on "Simulating Your Design."
(Xilinx Answer 20278) In a FIFO16-based FIFO Generator implementation, when the output depth is larger than the selected Input Depth, it is possible for PROG_EMPTY and PROG_FULL to produce false-assert values if the Programmable Empty or Programmable Full thresholds are near the limits of their range.
(Xilinx Answer 20291) During simulation, you might receive setup and hold time violations.
(Xilinx Answer 20271) When using Independent clocks with Block Memory type, you might see an error during back-annotated simulation (gate-level and timing) at the reset.
(Xilinx Answer 22014) Full width of data count is not available.