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AR# 21871

State Diagram Editor - Why are some of the outputs high during reset?

Description

Using the ISE State Diagram Editor to generate VHDL code, the State machine looks ok, but the generated VHDL code appears to have incorrect initialization of some signals. Should not every output be set to zero when reset is active?

Solution

Two cases will cause an output to be set to "1" when the asynchronous reset is applied: 

 

- If the signal is set to "1" in the first (reset) state of the state machine 

 

- If the signal is active LOW. In this case, when reset is applied, the active low signals will automatically be set to inactive state (HIGH)

AR# 21871
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article