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AR# 21874

7.1i Virtex-4 LogiCORE PCI - Does the PCI66/64 Core in a Virtex-4 require the Regional Clock option?

Description

General Description: 

Does the PCI66/64 for Virtex-4 rquire the Regional clock option? 

When using the PCI Core, what is the difference in the regional clock vs. the global clock?

Solution

For detailed information on the Virtex-4 regional clocking option, see the Virtex-4 User Guide at:  

http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides
Navigate to FPGA Device Families -> Virtex-4 -> Virtex-4 User Guide (UG070) -> Clock Resources -> Global and Regional Clocks. 

 

The information below specifically pertains to the PCI v3.0 Core: 

 

Global clock 

- familiar to customers from earlier families (e.g. Virtex-II/Pro) 

- only supports 33 MHz for Virtex-4 (both 32- and 64-bit interfaces) 

- unless special board considerations are made, locks the customer out of upgrading to 66 MHz without a board respin 

- user application design synchronous to bus clock may be larger due to larger reach of global clock (more resources available) 

 

Regional clock 

- required for 66 MHz for Virtex-4 

- provides easy upgrade from 33 MHz design 

- can be used for 33 MHz (both 32- and 64-bits) 

- some parts (e.g., XC4VFX60-FF672) do not have enough bonded I/Os within three adjacent clocking regions to do 66/64. This limits pin-out/package options. See the "Regional Clock Usage" section of the "PCI Getting Started User Guide." 

- user application design synchronous to bus clock is limited to logic reachable by regional clock signal (typically, the most severe issue is limited block RAM) 

 

BOTH the global and the regional clock versions have an extra pin (RCLK) to support IDELAY usage. This is new for Virtex-4 compared to other architectures. Again, BOTH the global and the regional clock versions require this RCLK. 

 

Note that the PCI-X Core uses the global clock, while the PCI Core has the provision for both regional and global. If you plan on doing a board design that uses both cores, global makes sense. Unless, you need 66 MHz when in PCI mode with the v3.0 Core. In that case, you must route the clock signal to both clock pins, which is not compliant but it does appear to work based on our testing with ML455. For more information on this board visit: 

http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-V4-ML455

AR# 21874
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article