Inside PACE, it is possible to perform a DRC using the Tools -> Run Design Rule Check (DRC) utility. However, when I run this utility for my Spartan-3E design, I receive the following error:
"<net_name>: Location constraint incompatible. Please check I/O Direction and IOB Type."
This is a known issue for certain Spartan-3E designs, and the error message usually indicates a clock input signal in the design is being LOC'ed to the GCK pin.
There are two suggested ways to work around this issue:
- Ignore this incorrect error in the PACE DRC algorithm. However, check to make sure no DRC warnings are reported by other Implementation Tools (look in the MAP Report and BitGen Report).
- Move the input to a different GCK location, if this is an option for your design.