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AR# 21918

LogiCORE SPI-4.2 (POS-PHY L4) v7.3 - Release Notes and Known Issues for the SPI-4.2 Core

Description

This Release Note is for the SPI-4.2 (POS-PHY L4) v7.3 Core released in 7.1i IP Update 3 and contains the following:

  • New Features
  • Bug Fixes
  • Known Issues

For the installation instructions and design tools requirements for 7.1i IP Update 3, see (Xilinx Answer 21938).

IMPORTANT: A patch is needed for all SPI-4.2 users targeting Virtex-4 devices, see (Xilinx Answer 22238).

Solution

New Features in v7.3

  • Support for DCM Standby Logic added
  • Option added to select DCM or PMCD for Sink core clocking
  • Option added to select DCM or PMCD for Source core clocking
  • Option added to bypass DCM or PMCD for TSClk global clocking

Bug Fixes in v7.3

  • CR 207107: GUI correctly allows SrcAFThresAssert and SnkAFThreshAssert to be less than 6
  • CR 208088: Removed unused RLOCs warnings in MAP
  • CR 208513: Correction made in the User Guide, DPA alignment time is 197 us, not 197 ms.

General Information

  • Version 7.3 of the SPI-4.2 Core supports only the Virtex-4 family. For Virtex-II and Virtex-II Pro devices, use the v6.x series of the SPI-4.2 Core.
  • Version 7.3 Core is compatible with ISE 7.1i Service Pack 3 and 4.
  • To migrate SPI4.2 design from v6.2 to v7.3 of the SPI-4.2 Core. (Xilinx Answer 21344)
  • To migrate SPI4.2 design from v7.2 to v7.3 of the SPI-4.2 Core. (Xilinx Answer 21967)
  • When to use Global Clocking vs Regional Clocking? (Xilinx Answer 21386)
  • When using Dynamic Phase Alignment or the SPI Core, RDClk must be running at least 220 MHz minimum.
  • What is the power consumption of SPI-4.2 Core? (Xilinx Answer 20430)
  • How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM? (Xilinx Answer 15500)
  • Which I/O Standards are supported for SPI-4.2 Core? (Xilinx Answer 20017)
  • If you are using multiple SPI-4.2 Cores in a single device, you must generate the core for each instance. See the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 User Guide.
  • When simulating an SPI-4.2 design with DCM standby logic, only timing simulation with SDF is supported. (Xilinx Answer 21959)
  • Source Core with Slave Clocking - use clocks from another Master Source core, not the general purpose clock from the sink core. (Xilinx Answer 22392)

Known Issues in v7.3

IMPORTANT: A patch is needed for all SPI-4.2 users targeting Virtex-4 devices, see (Xilinx Answer 22238).

Core Generation Issues

  • When using SPI-4.2 with greater than 900 Mbps, PMCD should not be used for clocking. (Xilinx Answer 22023)
  • When I generate an SPI-4.2 (PL4) Core through CORE Generator, the following errors occur:

    "ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\5_2i\pl4_core.asy does not exist."
    "ERROR: Did not generate ISE symbol file for core <pl4_core>." (Xilinx Answer 15493)

Constraints and Implementation Issues

  • When implementing an SPI-4.2 design through NGDBuild, several "WARNING" and "INFO" messages appear. (Xilinx Answer 20000)
  • When implementing an SPI-4.2 design through MAP, several "WARNING" and "INFO" messages appear. (Xilinx Answer 21439)
  • When implementing an SPI-4.2 design through PAR, several "WARNING" and "INFO" messages appear. (Xilinx Answer 21320)
  • For Virtex-4 design, PAR has problem completely routing the SPI4.2 design. (Xilinx Answer 21363)
  • Placement failures occur in PAR when the SPI-4.2 FIFO Status signals' I/O Standard is set to LVTTL I/O. (Xilinx Answer 20280)
  • Timing Analyzer (TRCE) reports "0 items analyzed." (Xilinx Answer 20040)
  • "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported." (Xilinx Answer 19999)
  • When running implementation, undefined I/O (single-ended) defaults to LVCMOS causing WARNINGS in NGDBuild. (Xilinx Answer 20319)
  • The SPI-4.2 Core signals default to LVDS without the internal device termination. If internal termination is needed, it must be defined in the UCF. In v7.3, this is predefined in the "wrapper.ucf" file. However, it needs to be uncommented. For a complete list of supported I/O, see (Xilinx Answer 20017).
  • When implementing an SPI-4.2 design through NGDBuild, an error occurs on the DIFF_TERM constraint. See (Xilinx Answer 21958).

General Simulation Issues

  • Using Dynamic Phase Alignment, PhaseAlignComplete signal is not asserted and SnkOof never gets de-asserted. (Xilinx Answer 21409)
  • When running timing simulation on a SPI4.2 Design Example, you might receive several "TDat Error: Data Mismatch" messages. (Xilinx Answer 21319)
  • When running timing simulation on a SPI4.2 design with Sink core set to Dynamic Alignment mode, you might receive several "Error: */X_ISERDES SETUP Low - - VIOLATION ON D WITH RESPECT TO CLK" messages. (Xilinx Answer 21321)
  • When running timing simulation on a SPI4.2 design, you might get several, SETUP, HOLD, and RECOVERY violations. (Xilinx Answer 21322)
  • When running Verilog timing simulation, TDat output is always "0000" and no training pattern is sent after reset. (Xilinx Answer 21362)
  • When simulating an SPI-4.2 design, multiple warning messages are expected at the beginning of the simulation. (Xilinx Answer 20030)
  • When simulating an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behavior occurs. (Xilinx Answer 15578)
  • When running timing simulation using the design example, DIP2 mismatch errors occur in the simulator. (Xilinx Answer 21316)
  • When simulating an SPI-4.2 design with DCM standby logic, only timing simulation with SDF is supported. (Xilinx Answer 21959)
  • When simulating an SPI-4.2 design with PMCD selected for internal clock, Error: Timing Violation Error : RST on instance * must be asserted for 3 CLKIN clock cycles. (Xilinx Answer 22023)

Hardware Issues

IMPORTANT: A patch is needed for all SPI-4.2 users targeting Virtex-4 devices,see (Xilinx Answer 22238).

  • When targeting Virtex-4 design with SPI4.2, be advised of silicon issue. (Xilinx Answer 20796)
  • When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations. (Xilinx Answer 20022)
  • An SPI-4.2 (PL4) Sink core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP4 error. (Xilinx Answer 15442)
  • When I open the SPI4.2 GUI in COREGen using the Hardware timeout evaluation license, it displays a pop-up message. The message indicates that the Hardware timeout lasts for 6-8 hours. However, the core will run only 2 hours.

SPI- 4.2 (PL4) v7.2 KNOWN ISSUES

  • The SPI-4.2 v7.2 Core is now obsolete. Please upgrade to the latest version of the core.

For information on existing SPI-4.2 v7.2 issues, see (Xilinx Answer 21032).

SPI- 4.2 (PL4) v7.1 KNOWN ISSUES

  • The SPI-4.2 v7.1 Core is now obsolete. Please upgrade to the latest version of the core.

For information on existing SPI-4.2 v7.1 issues, see (Xilinx Answer 20274).

AR# 21918
Date Created 09/04/2007
Last Updated 05/12/2012
Status Active
Type Release Notes
IP
  • SPI-4 Phase 2 Interface Solutions