Why do I have a cl_clr pin at the top level of my design? My design does not work in hardware after generating a bitstream from the Project Navigator Project when using the HDL Netlist flow or Bitstream flow. Why?
When System Generator for DSP 7.1 creates a design, it adds a ce_clr pin that is not necessary for most designs.
To work around this issue, use the HDL Netlist flow. Change the following line in the <design name>_clk_wrapper.vhd:
ce_clr_sysgen <= ce_clr;
ce_clr_sysgen <= '0';
This issue is addressed in System Generator for DSP 8.1.