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AR# 21936

7.1i EDK - Base System Builder (BSB) ML403 design does not work

Description

Keywords: timing, connection, connect, GDB

Urgency: Standard

General Description:
After downloading the design (implementation was done with ISE 7.1sp3), it did not work and a connection to the PPC was not made.

Solution

The timing report shows that timing (Reset Block) was not met. After adding the following TIGs, timing was met:

NET xxx/RSTC405RESETSYS TPTHRU = RST_GRP;
NET xxx/RSTC405RESETCHIP TPTHRU = RST_GRP;
NET xxx/RSTC405RESETCORE TPTHRU = RST_GRP;
NET xxx/C405RSTSYSRESETREQ TPTHRU = RST_GRP;
NET xxx/C405RSTCHIPRESETREQ TPTHRU = RST_GRP;
NET xxx/C405RSTCORERESETREQ TPTHRU = RST_GRP;
TIMESPEC TS_RST1 = FROM CPUS THRU RST_GRP TO FFS TIG;

where "xxx" stands for the instance name of EDK sub-module.

Additionally, the DCM which generates the 300 MHz CPU clock had to be set to the high frequency mode.

The parameter for the dcm_module in the MHS is as follows:

PARAMETER C_DFS_FREQUENCY_MODE = HIGH

After making these changes, the design runs on the ML403 with no problems.
AR# 21936
Date Created 08/17/2005
Last Updated 04/16/2007
Status Archive
Type General Article