AR# 21938


7.1i IP Update #3 CORE Generator - Release Notes and Known Issues for CORE Generator ISE 7.1i IP Update 3 (IP3_H)


Keywords: networking, Ethernet, MAC, XAUI, gigabit, SPI, SPI4, SPI42, SPI-4.2, SPI4.2, PL4, GFP, Tri-Mode, generic, framing, procedure, SONET, system, packet, interface, fibre, channel, DVB-ASI, FIFO, fifo16, cam, asynchronous, 8b10b, decoder, ip4_g, embedded, Aurora, wrapper, PCI, PCI-X, PCI32, PCI64, PCIX, counter, DSP, Binary Counter, Comparator, Complex Multiplier, Distributed Arithmetic FIR Filter, DVB S2 FEC Encoder, Floating-point Cores, MAC, MACC, Pipelined Divider, RAM-based Shift Register, TCC Encoder 3GPP, LogiCORE, COREGen, CORE, CORE Generator, generator

Urgency: Standard

General Description:

This Answer Record contains Release Notes for ISE 7.1i IP Update 3 (also known as IP3_H) and includes the following:

- Software and Tool Requirements
- Installation Instructions
- MXE Simulation Library
- Updated IP list
- Known issues

Main informational page on for this release:
For IP specific information see the Xilinx IP center web page:



The following is a listing of Release Notes and Known Issue links for IP included in this IP Update release:

- Release Notes and Known Issues for Dual Port Block Memory v6.3 (Xilinx Answer 21946)
- Release Notes and Known Issues for Embedded Tri-mode Ethernet MAC Wrapper v3.1 (Xilinx Answer 21903)
- Release Notes and Known Issues for FIFO Generator v2.2 (Xilinx Answer 21848)
- Release Notes and Known Issues for LogiCORE PCI/PCI-X and PCI/PCI-X UCF Generator (Xilinx Answer 21943)
- Release Notes and Known Issues for SPI-4.2 v7.3 (Xilinx Answer 21918)
- Release Notes and Known Issues for SPI-4.2 Lite v3.0 (Xilinx Answer 21919)
- Release Notes and Known Issues for SPI-3 PHY v4.0 (Xilinx Answer 21920)
- Release Notes and Known Issues for SPI-3 Link v4.0 (Xilinx Answer 21921)

- Release Notes and Known Issues for all DSP products (Xilinx Answer 21942)
Fast Fourier Transform v3.2
DVB S2 FED Encoder v1.0

Additional Release Notes and Known Issue Answer Records updated for IP3_H:

- Release Notes and Known Issues for LogiCORE Gigabit Ethernet MAC v6.0 (Xilinx Answer 21043)
- Release Notes and Known Issues for LogiCORE Tri-mode Ethernet MAC v2.1 (Xilinx Answer 21044)
- Release Notes and Known Issues for LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v6.0 (Xilinx Answer 21045)
- Release Notes and Known Issues for LogiCORE 10 Gigabit Ethernet MAC v6.0 (Xilinx Answer 21046)
- Release Notes and Known Issues for LogiCORE Ethernet Statistics v1.1 (Xilinx Answer 21055)
- Release Notes and Known Issues for LogiCORE Fibre Channel v2.0 (Xilinx Answer 21048)
- Release Notes and Known Issues for LogiCORE XAUI v6.0 (Xilinx Answer 21047)


General Known Issues

6.1i COREGen - CORE Viewer reports incorrect resource utilization for XST-based cores (Xilinx Answer 14676)
6.3i CORE Generator - "ERROR:NgdBuild:76" given for CORE Generator ".ngc" file (Xilinx Answer 20483)
7.1i CORE Generator - Some CORE Viewer data, from footprint, is not readable (Xilinx Answer 20692)
7.1i CORE Generator - COREGen will not launch. Error messages: "Could not reserve enough space for object heap" and "Could not create the Java virtual machine" (Xilinx Answer 20708)
7.1i CORE Generator - COREGen returns message "ERROR:coreutil:195 - Could not create Java virtual machine" - JVM (Xilinx Answer 20780)
7.1i CORE Generator - "ERROR:sim:4 - Could not create clean working directory \\<unc_path>\myproj\tmp\_cg." (Xilinx Answer 20721)
7.1i CORE Generator - No IP is available for Automotive parts (Xilinx Answer 20765)
7.1i CORE Generator (Japanese version) - If the underscore "_" character is used in a component name, the character is written out as a pipe character "|". For details on this possible naming issue when using a machine with a Japanese 106-character keyboard, see (Xilinx Answer 15312).
7.1i CORE Generator - Error occurred while executing formal verification script "core2formal_wrp" (Xilinx Answer 20715)
7.1i CORE Generator - Attempting to open a core customization GUI opens the data sheet for the selected IP core. (Xilinx Answer 21364)
7.1i HDL Parsers - "ERROR:HDLParsers:3281 - "<filename>" Line <line number>. behavioral is not an architecture body for <core_name> in library XilinxCoreLib" (Xilinx Answer 21938)


Install the IP Update using one of the following methods:

Method 1: Automated Update using the Updates Installer

1. Start the CORE Generator Update Installer (from the CORE Generator Main GUI, select Tools -> Update Installer).
If you are prompted for a proxy host, contact your administrator to determine the proxy host address and port number that you should be using to get through your firewall.
2. Select " ISE 7.1i IP Update 3 (FTP)," or " ISE 7.1i IP Update 3 (HTTP)" from the list of updates in the Available Packages panel, depending on which mechanism works best for you.
3. Click "Add To Install Queue" to add the zip file for the update to the install queue.
If you are prompted to enter a login name and password, use the Xilinx login and password that you normally use to download IP Updates and Service Packs.
4. Click "Install All Packages From Queue" to automatically initiate a download of the update.
After the update is downloaded, the Updates Installer displays a dialog box indicating that it is terminating the CORE Generator session and installing the downloaded archive. Another dialog box will indicate when the update installation is complete; you can then restart CORE Generator.
5. To confirm that you have installed the update properly, check the following file:

NOTE: This step assumes that your Xilinx design tools are installed in C:\Xilinx.

Method 2: Manual Installation

1. Close the CORE Generator application, if it is running.
2. Download the ".zip" file (PC) or "tar.gz" file (UNIX) from the following location and save it to a temporary directory:

NOTE: Before you can access this page and the files listed on it, you must be registered for CORE Generator IP Updates access.

3. Extract the ".zip" file (71i_ip_update3zip) or "tar.gz" (71i_ip_update3.tar.gz) archive to the root directory of your Xilinx design tools installation. Allow your extractor utility to overwrite all existing files and maintain the directory structure pre-defined in the archive.

Unzip the ".zip" file using WinZip 7.0 SR-1 or later. The Xilinx design tools installation directory is typically located at "C:\XILINX", if the installation defaults were used. You can verify the location of the Xilinx install by entering the following on the DOS command line:
echo %XILINX%

NOTE: When extracting the files using WinZip, you have to check the Use Folder Names option.

Use UnZip to unpack the ".zip" file. Xilinx recommends that you download the "tar.gz" file and unpack it using the UNIX command line gunzip and tar utilities. WinZip and GNU tar are not recommended for extracting the "tar.gz" archive because of differences in the way they handle files with long path names. See (Xilinx Answer 11162) for more details.

If you have already installed your Xilinx ISE design tools, the Xilinx installation directory location is the value of the XILINX variable, which is defined by your setup script. After sourcing your Xilinx setup script, enter the following to determine the location of your Xilinx installation:
echo $XILINX

You might need system administrator privileges to install the update.

4. Restart CORE Generator. During start-up, CORE Generator automatically detects that new IP has been added to your installation. It allows you to specify which IP customizers (cores) will be visible in your currently active CORE Generator project. For your current project, you can select the following:
- Display only the latest versions for "All" cores in the catalog.
- Update the catalog view to add only "New" cores to the display.
- Make a "Custom" selection of cores visible in the CORE Generator catalog display for your current project.

5. Determine whether the installation was successful by verifying that the new cores are visible in the CORE Generator GUI.


Supported Operating Systems

- Windows 2000 Professional (Service Pack 2 to 4)
- Windows XP Home (Service Pack 1)/Professional (Service Pack 1)
- Sun Solaris 8/9
- Linux Red Hat Enterprise 3.0 (32 bit and 64 bit)

Tool Requirements

To use this IP Update, first ensure that you have installed ISE 7.1i with Service Pack 4 (7.1i.04i) or later. ISE 7.1i Service Packs can be downloaded from the following page:

Acrobat Reader Requirement

Acrobat Reader Version 5 or later must be installed to view core data sheets. You can download the latest Acrobat software from the Adobe site:

To search for other available IP cores, go to:

If you have comments, questions, or problems, contact Xilinx Technical and Applications Support at:


What's New

Cores Included in this Release

The following link provides a list of all IP available with IP3_H. Any new cores or new versions of a core will be marked with an asterisk (*):

NOTE: IP Updates are cumulative (IP Update 3 contains all of the cores available in IP Update 1 and IP Update 2).

b>What's New in the CORE Generator application

- New C++-based IP customization GUIs available for most new core versions in this release load and display faster on your desktop.
- CORE Generator now passes device-specific data to the customization GUIs instead of just the device architecture family. This enables CORE Generator to optimize the generated core for the specific device and also prevents you from trying to generate a core that would be too large for a particular device.


MXE Simulation Library

The cores delivered with this IP Update require updated XilinxCoreLib libraries. For information on how to obtain the latest pre-compiled MXE libraries, see (Xilinx Answer 10616).
AR# 21938
Date 12/13/2006
Status Archive
Type General Article
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