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AR# 21959

LogiCORE SPI-4.2 (POS-PHY L4) - When simulating an SPI-4.2 design with the DCM Standby Logic, I might see "# ** Error: (vsim-3601) Iteration limit reached at time 0 ps."

Description

When simulating an SPI-4.2 design with the DCM Standby Logic, I must run timing simulation with the SDF file. If I try to simulate without the SDF file, I might receive an error during the simulation. The following error is seen from MTI simulator:

"# ** Error: (vsim-3601) Iteration limit reached at time 0 ps."

Solution

This issue is due to a ring oscillator in the DCM Standby Logic not toggling when used with UniSim simulation model. When using an SPI-4.2 Core with the DCM Standby Logic, the only way to simulate the core is to perform timing simulation which uses the SimPrim model, and you must simulate with the SDF file.

If you are not quite ready to perform timing simulation and would like to perform functional simulation, please use the SPI-4.2 Core without the DCM Standby Logic and replace it with the SPI-4.2 Core netlist with the DCM Standby Logic when you are ready to perform timing simulation. There are no functional differences between the two NGC netlists other than the DCM Standby Logic, and you should be able to simply replace the NGC netlist without making any design changes. Once the netlist is replaced, you will need to re-run the implementation from NGDBUILD command.

For more information on simulating the SPI-4.2, see the "Simulating and Implementing the Core" section of the SPI-4.2 User Guide:

http://www.xilinx.com/support/mysupport.htm

AR# 21959
Date Created 09/04/2007
Last Updated 05/03/2010
Status Active
Type General Article