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AR# 21971

ISE 7.1 MIG1.4 - Release Notes for Memory Interface Generator (MIG)

Description

This Answer Record contains the Release Notes for ISE 7.1i MIG 1.4, and includes the following: 

 

- Supported Operating Systems 

- Software and Tool Requirements  

- Installation Instructions  

- Getting Started

Solution

New or Modified Cores in This Release 

 

- MIG 1.4 Memory Interface Generator for Virtex-4 and Spartan-3/-3E devices 

 

Supported Operating Systems 

 

- Windows XP Home (Service Pack 1)/Professional (Service Pack 1) (32 bit) 

- MIG is not available on other ISE platforms 

 

Xilinx Design Tools Version Requirements 

 

To use this IP Update, first ensure that you have installed ISE 7.1i with Service Pack 4 (7.1i.04i).  

 

You can obtain ISE 7.1i Service Packs from the Download Center at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp  

 

MIG 1.4 requires ISE 7.1i IP Update 3 or later. If it has not already been installed, IP Update 3 is automatically installed by the Updates Installer before the ISE 7.1i MIG 1.4 IP Update is installed. See (Xilinx Answer 21938) for issues related to ISE 7.1i IP Update 3. 

 

Acrobat Reader Version 5 or later must be installed. You can download the latest Acrobat software from the Adobe Web site at: 

http://www.adobe.com/products/acrobat/readstep.html  

 

Installation  

 

Method 1 

Use this method if you are behind a firewall and do not know your proxy settings. 

 

1. Ensure that you have the latest ISE 7.1i Service Pack and the latest IP Update from the Download Center at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
 

- For ISE, you will receive an installer. 

- For the IP Update, you will receive a zip file that you must unzip into the 7.1i installation. 

- For MIG 1.4, ISE SP3 and the latest IP Update are required. 

 

2. If you are not registered for the Memory Corner, register at: 

http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=memory_customers
 

3. Download the MIG 1.4 from:  

http://www.xilinx.com/support/software/memory/protected/ise_71i_mig14.zip
(Enter your xilinx.com account name and password when prompted.) 

 

4. Unzip this file into the root ISE 7.1i installation (C:\Xilinx by default). 

 

Method 2 

 

1. Launch CORE Generator by selecting Start -> Xilinx ISE 7.1i -> Accessories -> CORE Generator from the Windows Start menu.  

2. When the CORE Generator GUI opens, select Tools -> Updates Installer. 

3. CORE Generator displays a dialog box with a warning indicating that it will exit after the installation is complete. Click the Accept button.  

4. CORE Generator connects you to www.xilinx.com and might ask for your xilinx.com User ID and password. If you are behind a firewall, you might have to enter the appropriate proxy settings. 

5. The IP Updates Installer dialog box opens and displays a panel listing the available updates.  

6. Select "ISE 7.1i MIG 1.4" and click the Install Selected button. The program might indicate that other installs are required. You can accept these informational messages. CORE Generator downloads and installs the requested products and exits. 

 

NOTE: Do not interrupt the installation process. During the process, you must accept various pop-up messages. If you have other windows open, the pop-ups might be hidden behind those windows. 

 

Getting Started  

 

To launch MIG, follow these steps: 

1. Launch CORE Generator by selecting Start -> Xilinx ISE 7.1i -> Accessories -> CORE Generator. 

2. Create a CORE Generator project. 

3. Set your Xilinx part correctly; it cannot be changed inside MIG. Note that Virtex-4 and Spartan-3/3E devices are supported by MIG. 

4. Remember the location of the CORE Generator project directory. The "View by Function" tab to the left shows the available cores organized into folders. 

5. Launch MIG by selecting Memories & Storage Elements -> MIG -> Memory Interface Generator. 

6. In the Module Name text box, enter the name of the module to be generated. When you click Generate, the module files are generated in a directory with the same name as the module name in the CORE Generator project directory.  

7. After generation, close the GUI by selecting the Dismiss button.  

 

The "Generated IP" tab to the left lists your generated modules. You can use the generated "ise_flow.bat" script or the ISE GUI to manually add the generated HDL files to a project. The MIG User Guide explains how the generated HDL files are used. You can access the MIG User Guide from the View Data Sheet links in CORE Generator, or from the Data Sheet button in the MIG GUI. 

 

Additional Information 

 

You can access additional MIG and memory-related information at: 

http://www.xilinx.com/products/design_resources/mem_corner/index.htm
 

NOTE: To access this URL, you must register specifically for the Memory Interface Generator product. 

 

See Memory Interface Generator (MIG) under the "Resources" section. 

 

You can search for other available IP cores at: 

http://www.xilinx.com/xlnx/xebiz/search/ipsrch.jsp  

 

If you have comments, questions, or problems, contact Xilinx Technical Support at: 

http://www.xilinx.com/support/techsup/tappinfo.htm 

 

What's New in MIG 1.4?  

 

New Features and Changes  

 

- Virtex-4 DDR1 SDRAM: 

* Supports both Verilog and VHDL. 

* XST synthesis. 

* By 8 and by 16 components. 

* All possible data widths. 

* No option to remove test bench and DCM. 

* CAS latency of three and burst length of four.  

* Verified in hardware with components. 

* May have issues with FIFO16 flags as described in (Xilinx Answer 22462)

 

- Virtex-4 DDR2 SDRAM: 

* VHDL added; supports both Verilog and VHDL. 

* Deep design added; verified in hardware with Verilog.  

* ODT and DCI verified with deep design.  

* May have issues with FIFO16 flags as described in (Xilinx Answer 22462)

 

- Spartan-3 DDR SDRAM:  

* Synthesis supported using Synplicity 7.7.1, Precision 2005b, and XST. 

* Verilog and VHDL. 

* By 8 and by 16 components, and unbuffered DIMMs. 

* All possible data widths. 

* Hardware tested using SL 361.  

* Verified with CAS latency three and burst length of four with test bench and DCM.  

* Tool supports only CAS latency of three. Design supports CAS latency of two if the configuration register values to be changed are as follows: assign u_config_parms = 10'b0000100010" in the test bench for CAS latency of two. 

 

- Spartan-3 DDR2 SDRAM: 

* Synthesis supported using XST. 

* Verilog and VHDL. 

* By 8 and by 16 components. 

* All possible data widths. 

* CAS latency of three and burst length of four. 

* No option to remove test bench and DCM. 

* Not hardware verified.  

 

- Spartan-3E DDR1: 

* Verilog and VHDL 

* XST 

* X8 and X16 components 

* Not hardware verified 

* Spartan-3E devices do not support top/bottom banks for data. There are not enough pins in the top/bottom banks to support DDR interface.  

 

Supported Devices 

- All Virtex-4 devices in all packages.  

- Most Spartan-3 devices are supported: 

* XC3S50 and XC3S200 are not supported since there are not enough pins to create a 16-bit interface. The PQ208 package is the one exception, but the rest of the package do not have enough pins. 

* XC3S2000FG456 and XC3S4000FG676 have been added.  

 

Software  

- Virtex-4 designs tested with ISE 7.1.04i. 

* May have issues with FIFO16 flags as described in (Xilinx Answer 22462)

- Spartan-3 design tested with Synplicity 7.7.1 and ISE 7.1.04i.  

 

NOTE: Timing has been verified for tool outputs with the ML 461 or SL 361 board configurations. 

 

What's New in MIG 1.3?  

 

Supported Devices 

- All Virtex-4 devices in all packages.  

- Most Spartan-3 devices are supported: 

* XC3S50 and XC3S200 are not supported, as there are not enough pins to create a 16-bit interface.  

* XC3S2000FG456 and XC3S4000FG676 will be supported in Release 1.4.  

 

Software  

- Virtex-4 designs tested with ISE 7.1.03i. 

- Spartan-3 designs tested with Synplicity 7.7.1 and ISE 7.1.03i.  

 

New Features and Changes 

- Integrated with ISE CORE Generator 7.1i. 

 

- Virtex-4 QDRII SRAM: 

* Verilog and VHDL support. 

* Hardware tested on ML 461 for all possible combinations. 

* Support for BL=2 and BL=4. 

 

- Virtex-4 DDRII SRAM: 

* Verilog and VHDL. 

* Not hardware verified. 

 

- Virtex-4 DDR2 SDRAM: Not available in MIG 1.3, but will be available in MIG 1.4 

* Support for up to eight controllers on the same device. 

* Hardware tested all possible cases using ML 461.  

* ECC support. 

* Supports No DCM and No Testbench. 

* Changed pin-out algorithm as follows: all DQ signals, DM signals and corresponding DQS signals are placed within the same bank. There is an exception for x4 DIMMs/components when the DM is associated with the second set of DQ/DQS signals, and it is possible that for the x4 case the DM signal is in a different bank compared to four of its corresponding DQ signals.  

* There is one pair of loop-back signals RD_EN_IN and RD_EN_OUT per bank. The input signal RD_EN_IN is used for all of the DQ signals in that bank.  

* One tap_ctrl module is instantiated per RD_EN pair; consequently, one tap_ctrl module per bank.  

* VHDL is not supported in this release and has been disabled.  

* Verilog deep design is not hardware tested.  

 

- Virtex 4 - RLDRAM II: 

* Supports both Verilog and VHDL 

* SIO and CIO 

* Multiplexed/Non-multiplexed address 

* All mode register variations 

 

- Virtex-4 DDR SDRAM: 

* Not supported in this release and has been disabled.  

 

- Spartan-3 DDR SDRAM: 

* Synthesis supported using Synplicity 7.7.1. 

* Hardware tested using SL 361. 

* Reduced read and write latencies. 

* Full controller functionality including auto-refreshes, and complete initialization. 

 

- Generation of board files for SL 361 or ML 361.  

 

General Issues Related to ISE 7.1.03i 

 

  • Timing errors. For signals crossing clock domains, this revision of the software analyzes timing paths with the calculated skew between the clocks.
    For example, for a path going from clk_div_16 to CLK, if there is a skew of 0.003 ns, the tools report errors based on this skew.
    The tools interpret the skew as the required time for the signals.
    This is an open software issue, and these errors may be safely ignored.  

  • Different signals for SR inputs of ODDR/IDDR. XST occasionally duplicates the reset signal to reduce the fanout.
    Consequently, it might assign different signals to the reset port of IDDR and ODDR.
    This can be avoided to some extent by increasing the XST fanout limit, and by turning off XST register duplication.
    However, Xilinx has observed these failures in rare cases even after changes have been made.  

 

NOTES: 

1. Timing has been verified for tool outputs with the ML 461 or SL 361 board configurations.  

2. The board files generated by MIG require an external clock source.

AR# 21971
Date Created 09/04/2007
Last Updated 09/04/2014
Status Active
Type General Article
Devices
  • Spartan-3
  • Virtex-4
  • Virtex-4Q
  • Spartan-3E
Tools
  • ISE - Legacy
IP
  • MIG