When I simulate my design example, I receive the following error for timing simulations:
"Note: RStat Error : DIP2 error received. Expecting 01, received 00. SnkDip2ErrReqFlag = 0"
The error occurs because the RStat checking is performed on the rising edge of RSClk. The mismatch errors occur because the RStat signal is transitioning at the clock edge. If you are using the simulation testbench provided with the SPI-4.2 Lite Core design example, this error can be ignored.
The testbench delivered with the SPI-4.2 Lite core is fixed in v4.2.