We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 21983

LogiCORE Binary Counter v8.0 - I cannot find the Verilog behavioral simulation model for the Binary Counter; when performing a Verilog behavioral simulation, I receive "Error: (vsim-3033) ... The design unit was not found"


Keywords: CORE, CORE Generator, COREGen, VSIM, template, VEO

I have generated a Binary Counter using the Verilog flow, and the VEO template file is created. However, I cannot find a Verilog simulation model. Why? Also, why does the following error occur when I perform a Verilog behavioral simulation?

"Error: (vsim-3033) ... The design unit was not found"

When I perform a Verilog behavioral simulation of the Binary Counter Core v.8.0, the following error occurs:

# ** Error: (vsim-3033) top_count.v(44): Instantiation of
> 'C_COUNTER_BINARY_V8_0' failed. The design unit was not found.
> # Region: /top_test1_v/uut
> # Searched libraries:
> #
> C:\Modeltech_6.0axe\win32xoem/../xilinx/verilog/xilinxcorelib_ver
> #
> C:\Modeltech_6.0axe\win32xoem/../xilinx/verilog/unisims_ver
> # work
> # Loading work.glbl
> # Error loading design

However, CORE Generator produces a Verilog wrapper file for simulation purposes (*.v file). Why does this occur?


The Binary Counter does not have a Verilog behavioral model. The supported language for behavioral simulation is VHDL. If your simulator does not support multiple languages, you can work around this issue by generating a Verilog structural model with ISE 7.1i or above.

For more information, please see (Xilinx Answer 22333).
AR# 21983
Date 07/12/2007
Status Archive
Type General Article
Page Bookmarked