In Table 5-10 of the PIPE UG and Table 4-8 of the v2.1.1 UG, bits 1 and 0 of the "cfg_command" register output from the core are marked reserved. Is this correct?
These bits have the same meaning in PCI Express as they do in PCI. Please see section 6.2.2 of the v3.0 PCI Specification for a detailed explanation of these bits.
Bit 1 enables the device's ability to respond to memory request, and bit 0 enables the device's ability to respond to I/O request. If these bits are not set, the core will not respond to memory or I/O write and read commands.
These bits are set by the host by issuing configuration writes to the command register located in the PCI configuration space at address 0x04.