When using the Embedded Tri-mode Ethernet MAC Wrapper v3.1 with the RGMII v2.0 interface at 10 Mbps 100 Mbps, or Tri-speed rates (not 1000 Mbps), the generated VHDL wrappers use an incorrect clock management for the TX RGMII logic is incorrect. Specifically, there is an extra BUFG used in the TX clock management, which needs to be removed, and the registers on the RGMII_TXC signal need to be clocked by CLK0 rather than CLK90 of the DCM .
Note that this does not affect the Verilog wrappers or if VHDL RGMII v2.0 is used with the 1000 Mbps speed setting.
A patch is available which corrects the TX RGMII clocking of the RGMII v2.0 interface in the VHDL version of the wrappers. To obtain this fix, install the patch that is available in the Embedded Tri-mode Ethernet MAC Wrapper v3.1 Core Release Notes and Known Issues Answer Record (Xilinx Answer 21903) and then regenerate the wrappers.