AR# 22027

LogiCORE SPI-3 LINK Layer Core v4.0 - PAR "INFO:Par:62 - My design did not meet timing (also applies to SPI-3 PHY Layer Core)"

Description

General Description:

When I run PAR with SPI-3 Core, I receive the following error from PAR:

"INFO:Par:62 - Your design did not meet timing.

Timing constraint: COMP "DTPA(29)" OFFSET = IN 3 ns BEFORE COMP "TX_CLK";

1 item analyzed, 1 timing error detected. (1 setup error, 0 hold errors)

Minimum allowable offset is 4.935ns.

--------------------------------------------------------------------------------

Slack: -1.935ns (requirement - (data path - clock path - clock arrival + uncertainty))

Source: DTPA(29) (PAD)

Destination: spi3_link_tx0/spi3_link_test_s373871_68/spi3_link_test_s373871_68_spi3_link_tx/spi3_link_test_s373871_68_spi3_link_tx_xst/U0/tx_flow0/dtpa_s1_29 (FF)

Destination Clock: tx_clk_int rising at 0.000ns

Requirement: 3.000ns

Data Path Delay: 6.624ns (Levels of Logic = 0)

Clock Path Delay: 1.689ns (Levels of Logic = 2)

Clock Uncertainty: 0.000ns

Data Path: DTPA(29) to spi3_link_tx0/spi3_link_test_s373871_68/spi3_link_test_s373871_68_spi3_link_tx/spi3_link_test_s373871_68_spi3_link_tx_xst/U0/tx_flow0/dtpa_s1_29

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

D19.ICLK1 Tiopickd 6.624 DTPA(29)

DTPA(29)

DTPA_29_IBUF

DTPA(29).DELAY

spi3_link_tx0/spi3_link_test_s373871_68/spi3_link_test_s373871_68_spi3_link_tx/spi3_link_test_s373871_68_spi3_link_tx_xst/U0/tx_flow0/dtpa_s1_29

------------------------------------------------- ---------------------------

Total 6.624ns (6.624ns logic, 0.000ns route)

(100.0% logic, 0.0% route)

Clock Path: TX_CLK to spi3_link_tx0/spi3_link_test_s373871_68/spi3_link_test_s373871_68_spi3_link_tx/spi3_link_test_s373871_68_spi3_link_tx_xst/U0/tx_flow0/dtpa_s1_29

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------

AK16.I Tiopi 0.578 TX_CLK

TX_CLK

TX_CLK_IBUFG

BUFGMUX0.I0 net (fanout=1) 0.001 TX_CLK_IBUFG

BUFGMUX0.O Tgi0o 0.286 txbufg

txbufg

D19.ICLK1 net (fanout=148) 0.824 tx_clk_int

------------------------------------------------- ---------------------------

Total 1.689ns (0.864ns logic, 0.825ns route)

(51.2% logic, 48.8% route)

--------------------------------------------------------------------------------"

Solution

Sometimes, a delayed IOB is selected by the tools, causing input timing to fail. Add a constraint to the project's UCF.

Ex: COMP "DTPA(29)" IOBDELAY=NONE ;

AR# 22027
Date 12/15/2012
Status Active
Type General Article