We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 22043

LogiCORE SPI-3 PHY Layer Core v4.0 - "ERROR:Place:207 - SelectIO banking constraints" (also applise to SPI-3 Link Core)


General Description:

My SPI-3 PHY design fails to route due to SelectIO banking constraints. the following PAR error occurs:

"Starting Placer

Phase 1.1

ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed."


This error occurs for systems with a large number of channels.

The example design has the user interface LocalLink signals coming out of the top level entity. The fact that they come out of the example design creates a large number of pins for SPI-3 Cores with a large number of channels. This causes MAP and PAR failures because there are not enough pins to support the number of pins on the SPI-3 Core.

This will not be an issue when you integrate the cores into your design because the LocalLink pins will not be going to the chip I/O.

AR# 22043
Date 12/15/2012
Status Active
Type General Article