My SPI-3 PHY design fails to route due to SelectIO banking constraints. the following PAR error occurs:
ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed."
This error occurs for systems with a large number of channels.
The example design has the user interface LocalLink signals coming out of the top level entity. The fact that they come out of the example design creates a large number of pins for SPI-3 Cores with a large number of channels. This causes MAP and PAR failures because there are not enough pins to support the number of pins on the SPI-3 Core.
This will not be an issue when you integrate the cores into your design because the LocalLink pins will not be going to the chip I/O.