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AR# 22103

NetGen - If hierarchy is kept, a Global_logic0/Global_logic1 is generated without a driver in the timing simulation netlist


The Global_logic0/Global_logic1 should be connected to the X_ZERO/X_ONE components. However, when the hierarchy is maintained, NetGen sometimes does not make this connection and signals that should be Global_logic0 are all "U" in timing simulation.


To work around this issue, flatten the design.

This issue is fixed in ISE 8.1i Service Pack 2, released in February 2006.

The following environment variable must be set when using ISE 8.1i Service Pack 2 and above:


AR# 22103
Date 12/15/2012
Status Active
Type General Article
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