When I am configuring a Spartan-3E via JTAG with the mode pins set to BPI mode, the device configuration fails. Why does this occur?
NOTE: This issue is addressed and fixed starting in the ISE 9.1.01 SW release, which has been available since January 2007.
There is a known issue when attempting to configure a Stepping 0 and Stepping 1 Spartan-3E FPGAs via JTAG when the FPGA mode pins are set for one of the BPI configuration modes.
NOTE: This issue applies to Spartan-3E engineering samples and to Stepping 0 and Stepping 1 devices.
Conditions Required to Generate the Issue:
- The Spartan-3E FPGA must be either a Stepping 0 or 1 device.
- The FPGA mode pins must be set for one of the BPI configuration modes (M[2:0] = <0:1:0> or <0:1:1>).
- The attached parallel NOR Flash contains a valid FPGA configuration image.
- When attempting to configure the Spartan-3E via JTAG, configuration fails.
- The FPGA fails to configure. The DONE pin is Low. The INIT_B pin is Low, indicating a configuration failure.
- Internal contention might be caused by the failed configuration. The FPGA might heat up.
As mentioned above, the issue is fixed in design tools, starting with the ISE 9.1.01i release. If you must use ISE 8.2.03i or earlier, there are two ways to work around this issue.
OPTION 1: When configuring the FPGA via JTAG, set the mode pins for JTAG mode (M[2:0] = <1:0:1>).
OPTION 2: When generating the bitstream that is ultimately stored in the attached parallel NOR Flash, offset the initial address by 0x2000. JTAG configuration will work properly. BPI Flash configuration also operates correctly but will require slightly more configuration time. The FPGA searches through the Flash image until it finds the appropriate synchronization word, now offset by 0x2000.