UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22224

Virtex-II Pro MGT - Does the silicon support a single-ended BREFCLK?

Description

General Description:

When I try to map a design with a single-ended BREFCLK, I receive the following error:

ERROR:LIT - BREFCLK2 of GT symbol "MY_MGT_INST" is chosen and must be driven by differential input buffer. The current driver of this pin is pin O of IBUF symbol "BREFCLK_IBUF" [output signal=brefclk).

Is this due to a software limitation or lack of silicon support?

Solution

The silicon will not support a single-ended BREFCLK. A differential input must be used for this signal.

AR# 22224
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article