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AR# 22255

Spartan-3 Configuration - JTAG configuration completes successfully, but the device is not fully operational or a verify fails


When operating on a Spartan-3/-3E/-3A device via JTAG, programming succeeds, but the design fails to work. If a "Verify" is performed, this fails as well. This occurs when the PROM is programmed with a different image than what is being loaded in the FPGA, and the FPGA is in master mode.


Explanation of the problem:
The problem is that iMPACT causes the mode pins to be sampled. If the device is in master mode, the CCLK is produced and the PROM begins to load the device with data. This occurs before iMPACT issues the instruction to begin configuration. When this happens, the JTAG logic gains control over the configuration logic and loads the device with the bitstream. The fabric of the Spartan-3/-3E FPGA must be initialized before it can be written over, so frames that have been written to by the PROM will not configure correctly. The CRC check passes as this occurs, while data is passed into the device.
The device goes through the start-up sequence, DONE goes High, and the device becomes operational. The problem is that the first few frames of the device have been corrupted and the design might not work successfully, and a verify with iMPACT fails.

Erase the flash or change the Mode pins to JTAG to work around this issue.
AR# 22255
Date 03/01/2013
Status Active
Type General Article
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