UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22271

8.1i XST - "FATAL_ERROR:Xst:Portability/export/Port_Main.h:<numbers>"

Description


While running synthesis on my design, the following fatal error occurs:



"FATAL_ERROR:Xst:Portability/export/Port_Main.h:<numbers>"



Xilinx is actively trying to provide better error messages to help you debug the issue. This Answer Record contains some of the solutions that have fixed the fatal error.

Solution


Below are some reasons why this error might occur, and the solutions that have fixed the error:



Case 1:



A port mismatch in the instantiation



An example snippet is below.



The following ports:

rdaddress : in std_logic_vector(R_DATA_WIDTH-1 downto 0);

rddata : out std_logic_vector(R_ADDRESS_WIDTH-1 downto 0)



were changed to:

rdaddress : in std_logic_vector(R_ADDRESS_WIDTH-1 downto 0);

rddata : out std_logic_vector(R_DATA_WIDTH-1 downto 0)



This fixed the problem.



This issue is fixed in ISE 8.2i.



Case 2:



A port in the module declared as INPUT is connected to a port in another module declared as INOUT but is used only as input.



XST is not detecting this illegal configuration and keeps the signal dangling. When flattening the hierarchy, the data structure is corrupted and results in an internal error. However, when the hierarchy is retained, XST builds each module separately and the problem is detected later in NGDBuild and MAP reports.



You can work around this issue by connecting these ports correctly: input to input and inout to inout.



This issue is fixed in ISE 8.2i.



Case 3:



This issue has also been seen if you name a hierarchical module with a Xilinx Primitive name. One observed case is when a block is named as a MUXCY, and the XST packer recognizes the block as a MUXCY primitive, leading to a fatal error.



You can work around this issue by not using any of the Xilinx Primitive names for user modules and hierarchies.



This issue is fixed in the ISE 8.2i.



Case 4:



A large number of muxes that constitute combinatorial loops (mux extraction cannot handle them properly).



This can be noted by examining the XST log file and looking for:



"WARNING:Xst:2170 - Unit RS_X16Y4_V1R3 : the following signal(s) form a combinatorial loop: X13Y3/XROUTING/XD/XO/Mmux_O_N2, X8Y3/Z, X8Y3/XROUTING/XD/XO/Mmux_O_N1, X15Y3/XROUTING/XD/XO/Mmux_O_N6, X15Y3/XROUTING/XD/XO/Mmux_O_N1, X13Y3/XROUTING/XD/XO/Mmux_O_N1, X13Y3/D, X8Y3/D, X15Y3_W8O."



You can work around this issue by setting the mux extraction option to "no." To learn more about this option, refer to the XST User Guide:

http://www.xilinx.com/support/software_manuals.htm


To access this manual:

1. In the Software Manuals page, under Current Software Manuals, click the appropriate link (depending on the design tools).

2. In the next page, click the PDF Collection link.

3. In the next page, click the Bookmarks tab on the left. Under Software Manuals, select the XST User Guide near the bottom of the tree.



This issue is scheduled to be fixed in ISE 9.1i.



Case 5:



This issue has also been noted when you infer a Dual Port Distributed RAM and a Dual Port Block RAM and instantiate these two components in the top level.



You can work around this by instantiating the Dual Port Distributed RAM in the first place, and then instantiate the Dual Port Block RAM.



Xilinx is currently investigating this issue.



Case 6:



This issue has also been observed when using incremental synthesis. You can work around the problem by disabling incremental synthesis, as described below:

-- attribute incremental_synthesis: string;

-- attribute incremental_synthesis of incremental: entity is "yes";

OR

attribute incremental_synthesis: string;

attribute incremental_synthesis of incremental: entity is "no";



Xilinx is currently investigating this issue.



Case 7:



You can work around this issue by turning off the RAM extraction in the Synthesis properties (right-click on Synthesize - XST => Properties => HDL Options => Do not select RAM Extraction).



This issue is fixed in the ISE 8.2i.



Case 8:



This has also been noted in a design where a KEEP property was applied to a signal that was never used in the design.



To work around this issue, remove the KEEP property from this unused signal.



Xilinx is currently investigating this issue.



Case 9:



Two signals are tied to ground in the top level. If you add ports to these signals so they are not always tied to ground, then the fatal error goes away.



This issue is scheduled to be fixed in ISE 9.1i.



Case 10:



The file-defining package is included in the ".prj" file, but not the one defining the package body.



XST crashes when looking for the package body in a function call.



This issue is fixed in the ISE 8.2i.



Case 11:



A multiplier, followed by a reg connected back on the mult input. XST tries to absorb the same reg both on input and output of the multiplier, resulting in an internal error.



To work around this issue, add a keep property, which prevents XST from absorbing reg on input or on output:

A keep on output of multiplier results in XST absorbing reg on input.

A keep on input of multiplier results in XST absorbing reg on output.



This issue is fixed in the ISE 8.2i release.



Case 12:



This error occurs on Windows only, when an old XST directory is not cleaned up.



To work around this issue, clean up the project files. For information on cleaning up project files, refer to the ISE Help.



Case 13:



In the design, there is a type that is a record with only one field, and when XST tries to perform the auto-RAM extraction, it crashes.



To work around this issue, replace the record with one field by the field itself.



This issue is fixed in ISE 8.2i.



Case 14:



This has been observed in some cases when the "Generate RTL Schematic" property is set to "Yes."



This issue can be worked around by setting the "Generate RTL Schematic" property to "No" in ISE. Refer to the ISE Help for details.



This issue is fixed in ISE 8.2i.



Case 15:



This has been observed when a mistake was made by assigning internal signals that are never driven in the design and they are optimized out.



To work around this issue, comment out this assignment.

This issue is fixed in ISE 8.2i



If these solutions do not help you resolve the problem, open a WebCase with Xilinx Technical Support at:

http://www.xilinx.com/support/clearexpress/websupport.htm
AR# 22271
Date Created 09/04/2007
Last Updated 06/28/2010
Status Archive
Type General Article