UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22289

7.1i Timing Analyzer - Different Tdcmino reported for the same DCM on OFFSET IN constraints

Description

Urgency: Hot

General Description:

I have two inputs in my design clocked by the same source clock, through a DCM. On these inputs I have defined some specific OFFSET constraints. When I look in the Timing report, I can see that the DCM parameter "Tdcmino" in clock path is different for the two inputs. When is this going to be fixed?

Solution

This is scheduled to be fixed in the next major release of the design tools.

AR# 22289
Date Created 09/04/2007
Last Updated 01/18/2010
Status Archive
Type General Article