The offset OUT constraint applied to the outputs of my design are not being analyzed.
The PAR reports the following:
"WARNING:Timing:2666 - Constraint ignored: TIMEGRP "group_name" OFFSET = OUT X ns AFTER COMP "Clk";"
How can I resolve this issue?
This behavior can be observed in designs where specific I/O standards are used to configure the outputs; for example, LVPECL.
Some delay information related to the I/O standard might be missing in the speedfiles.
To work around the problem, use the LVTTL I/O standard and the I/O adjustment table in the target device's DC and Switching Characteristics Data Sheet to set the correct OFFSET requirement.
This behavior can be observed in designs when another OFFSET constraint, or FROM:TO constraint, cover the same paths as the OFFSET constraint in question. Run a Time Spec Interaction Report (TSI) to determined which constraints interact with this OFFSET constraint.