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AR# 22319

LogiCORE RapidIO v3.1 Rev 2 - Release Notes and Known Issues for 8.2i IP Update 1 (8.2i_IP1)

Description

This Answer Record contains Release Notes and Installation information for the LogiCORE RapidIO Core v3.1 Rev 2 Release.

Serial RapidIO and Logical Layer cores are available in IP Update #1 (8.2i IP Update 1). This update must be downloaded and installed on top of your current ISE 8.2i design tools. See (Xilinx Answer 23479) for general information about this update. You can access this update at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp.

Updates for the Parallel RapidIO Physical Layer

To obtain the latest version for the Parallel RapidIO Physical layer, go to the Xilinx RapidIO lounge at:

http://www.xilinx.com/rapidio

NOTE: If you are using the Parallel RapidIO Physical Layer, you should also use the Design Environment and Logical Layer available for download from the RapidIO lounge and not the ones available through CORE Generator provided in the section above. This is necessary because the Logical Layer and Design Environment provided through CORE Generator are tested and supported only by the Serial RapidIO Physical layer, also available through CORE Generator.

Solution

New Features in v3.1 Rev. 2

- Support Added for ISE 8.2i

Serial RapidIO Physical Layer

- Additional ports added to allow you to protect against Virtex-4 static operating behavior MGT issues as described in (Xilinx Answer 22471). The use of these new signals is further described in Chapter 7 of the Serial RapidIO User Guide. This document is generated along with the core.

- Added support for increased reference clock frequencies to allow for reduction of transmit jitter. Clock frequency requirements are further defined in Chapter 7 of the Serial RapidIO User Guide. This document is generated along with the core.

RapidIO Logical and Transport Layer

Receive side Byte enables from the logical layer have been modified. Actual byte counts are now indicated on the iresp_byte_count, treq_byte_count, and mreq_byte_count ports for sub-dword packets.

Known Issues in v3.1 Rev. 2

Serial RapidIO Physical Layer

- When targeting the Virtex-4 device and operating in x4 mode, the core is not capable of training down to single-lane operation on lane 2. However, the core does train down and operate in single-lane mode on lane 0.

- When targeting the Virtex-II Pro device, if the core is forced into x1 mode on lane 0 via a write to the Port Control CSR, the core still initializes into x1 mode on lane 2 if lane synchronization cannot be obtained on lane 0.

- Corrupted or repeated packets occur on data. See (Xilinx Answer 24500).

- The core netlist cannot be loaded into PlanAhead. See (Xilinx Answer 24501).

- Repeated packet can be seen upon RETRY. See (Xilinx Answer 24527).

- Stomped packet incorrectly sent after Restart-from-Retry control signal causing protocol error (Packet Not Accepted). See (Xilinx Answer 24837).

- x1 Core is unable to train when connected to x4 Core when targeting Virtex-5 or Virtex-II Pro. See (Xilinx Answer 24838).

(Xilinx Answer 30023) x4 core can train down to x1 using lane 0, but not to other lanes

(Xilinx Answer 30314) Virtex-4, x4 Core might intermittently train down to x1 due to MGT lock signal issue

(Xilinx Answer 30054) CAR value incorrect

(Xilinx Answer 30323) Re-initialization is not forced following a change to Port Width Override

RapidIO Logical and Transport Layer

- When the user application is idle, it must keep iresp_rdy_n and treq_rdy_n asserted for the core to assert iresp_sof_n and treq_sof_n, respectively. If these signals are not asserted, the core will not present new packets to the user.

- Logical Layer- Full 16-bit device ID is not usable. See (Xilinx Answer 24498).

- Transmit port can result in lock-up. See (Xilinx Answer 24497).

(Xilinx Answer 30320) Messaging packet has incorrect treq_byte_count

(Xilinx Answer 29936) Maintenance RESPONSE packet has incorrect source device ID

(Xilinx Answer 30322) Missing EOF or missing packet on target request interface when sending 8-byte SWRITE

RapidIO Buffer Layer

- Packets corrupted in the buffer. See (Xilinx Answer 24499).

- The buffer can go into a permanent stall state if the current packet is discontinued and there is no lnk_next_fm change. See (Xilinx Answer 24844).

Design Environment

- When simulating the design example, Memory Collision Error can be seen. See (Xilinx Answer 24366).

- When simulating the design example on PC, will need to edit simulate_mti.do file. See (Xilinx Answer 23961).

Previous Release Information

New Features in v3.1 Rev. 1

- Support for 8.1i SP3. Note 8.1i SP3 is required for all Virtex-4 RapidIO designs as of the v3.1 Rev. 1 release.

- Support for Virtex-4 FX ES4 Stepping: Virtex-4 FX cores include Calibration Block 1.4.1 to support CES4 silicon stepping.

- Added critical request flow functionality.

- Retransmit suppression support.

- Full support of doorbell and messaging.

- All layers enhanced to run at 156 MHZ for full support of 3.125 GHz per lane.

Known Issues in v3.1 Rev. 1

Serial RapidIO Physical Layer

- When targeting the Virtex-4 device and operating in x4 mode, the core cannot train down to single-lane operation on lane 2. However, the core does train down and operate in single-lane mode on lane 0.

- When targeting the Virtex-II Pro device, if the core is forced into x1 mode on lane 0 via a write to the Port Control CSR, the core still initializes into x1 mode on lane 2 if lane synchronization cannot be obtained on lane 0.

- The core currently does not protect against the RocketIO MGT Static Operating Behavior problem described in EN042 (Errata for Virtex-4 CES4 devices). For more information on this problem, see (Xilinx Answer 22471). The core does contain calibration block version 1.4.1, but it is currently not being used to protect against this problem; this will be fixed in a future release. Do not hold the core in reset for extended amounts of time or use the x4 core in single lane mode for extended amounts of time.

- The following "Port Configuration" options must be set for successful simulation of the example design accompanying the core. These are limitations of the example simulation environment and not an issue with the core:

Master - enabled

Port Disable - disabled

- The "srio_phy_4x_ep_4vpfx60ff1152.ucf" file in the Design Environment templates directory targets a period of 6.2 ns to illustrate that the core operates with margin. Customer designs should use a 6.4 ns value corresponding to 156.125 MHz operation.

RapidIO Logical and Transport Layer

- The following RapidIO Logical Layer option must be set for successful simulation of the example design accompanying the core. This is a limitation of the example simulation environment and not an issue with the core:

Local Configuration Space Base Address - 0x7FFXXXXX

RapidIO Design Environment

- VHDL is not supported at this time. The functional simulation models for the Serial RapidIO Physical Layer and RapidIO Logical Layer cores are generated in VHDL if VHDL is selected in the CORE Generator Project Properties. However, the RapidIO Endpoint example design, including the Buffer and Register Manager reference design files, are in Verilog. Consequently, the implementation and simulation scripts support only Verilog.

- The Serial RapidIO Physical Layer, RapidIO Logical Layer, and RapidIO Design Environment cores must all be generated from within the same CORE Generator project directory to ensure the functionality of the implementation and simulation scripts.

- The "Serial PHY Layer" entry must match the component name given to the Serial RapidIO Physical Layer core during generation. Also, the "Lanes" and "Baud Rate" must match what was selected when the Serial RapidIO Physical Layer core was created. This is necessary to ensure the functionality of the implementation and simulation scripts.

- The "Logical Layer" entry must match the component name given to the RapidIO Logical Layer core during generation to ensure functionality of the implementation and simulation scripts.

AR# 22319
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article