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AR# 22322

LogiCORE PCI Express PIPE v1.5 - Release Notes and Known Issues for 8.2i IP Update 2 (8.2i_IP2)

Description

This Answer Record contains Release Notes and installation information for the LogiCORE PCI Express PIPE Core v1.5 release.

Solution

A CORE Generator update (8.2i IP Update 2) is available for the pci_exp_1_lane_32b_pipe_ep core. This must be downloaded and installed on top of your current 8.2i design tools. For general information about this update, see (Xilinx Answer 23831). This update is located at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp.

-Refer to the NXP data sheet for PX1011B errata items. PX1011B errata items are included in section 14 of the data sheet.

This data sheet is found at:

http://www.nxp.com/acrobat_download/datasheets/PX1011B_4.pdf
NXP Product Page:

http://www.nxp.com/#/pip/pip=[pip=PX1011B_4]|pp=[t=pip,i=PX1011B_4]

Known Issues v1.5

- See (Xilinx Answer 23823) for timing issues related to the selected part during XST synthesis.

- PCI Express PIPE Endpoint Core does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging and is not needed for normal operation.

Previous Release Information

v1.4 Revision 1

To download v1.4 Revision 1, click the following link:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/pci_express_pipe_v1_4_rev1.zip

This revision should be installed only on top of 8.2i IP Update 1. To install 8.2i IP Update 1, first ensure that 8.2i sp1 has been installed. Once 8.2i sp1 has been installed, obtain the IP Update and install it on top of the 8.2i sp1 installation. For general information about the 8.2i IP Update 1, see (Xilinx Answer 23479). Service packs and the IP Update are located at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

To install this update, unzip the file into your current Xilinx install directory as pointed to by your Xilinx environment variable. You might be prompted to allow the update to overwrite existing files. Select "Yes to All." Ensure that the 8.2i IP Update 1 is already installed.

New Features v1.4 Revision 1

- None.

Known Issues v1.4 Revision 1

- See (Xilinx Answer 23823) for timing issues related to the selected part during XST synthesis.

- PCI Express PIPE Endpoint Core does not implement "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging and is not needed for normal operation.

Fixed Issues v1.4 Revision 1

- CR 235976: Improved timing closure for xc3s1500, xc3s4000, xc3s5000, xc3s1200E, xc3s1600E

New Features v1.4

- Support added for ISE 8.2i.

- New cfg_dsn input port. The user application drives this port with a unique 64-bit Device Serial Number.

- Added support for Spartan-3E -4 device speed grade.

- Includes a PCI Express Downstream Port functional simulation model as part of the user test bench.

General Information v1.4

- Power Consumed and Power Dissipation GUI parameters are now entered in decimal and not hexadecimal.

- A new input port called cfg_dsn has been added to the core. This replaces the Device Serial Number field that was in the GUI. The device serial number is now an input port to the core, so you can change the number without needing to re-generate the core. For more information on the device serial number, refer to section 7.12.2 of the PCI Express Base Specification.

- As a result of the above two changes, existing v1.3 CORE Generator XCO files will not allow generation of a v1.4 core with the same parameters. A Perl script is provided so you can migrate your existing XCO file to a v1.4 compatible XCO file. This script changes the power consumed and power dissipation parameters to decimal, changes the core version to v1.4, and "comments out" the device serial number parameter. This script is located at:

http://www.xilinx.com/txpatches/pub/utilities/fpga/pcie_xco_ver_migrate.zip

Known Issues v1.4

- PCI Express PIPE Endpoint Core does not implement "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging and is not needed for normal operation.

New Features v1.3 Revision 2

- Added 8.1i Service Pack 3 support.

Obtaining v1.3 Revision 2

- This revision can be obtained at:

http://www.xilinx.com/txpatches/pub/swhelp/coregen/pci_express_pipe_v1_3_rev2.zip

- To install this update, unzip the file into your current Xilinx install directory as pointed to by your Xilinx environment variable. You might be prompted to allow the update to overwrite existing files. Select "Yes to All." Ensure that 8.1i IP_1i is already installed. Note that it is not necessary to install the revision 1 update file before installing the revision 2 update. The revision 2 update includes all features and fixes that were included in revision 1. Do not install v1.3 rev2 on top of 8.2i IP Update 1 software. This version can be installed only on 8.1i IP Update 1.

Fixed Issues v1.3 Revision 2

- CR 228948: Time-out Update FC DLLPs for Posted and Non-Posted credit queues is transmitted more often than recommended by the specification.

Known Issues v1.3 Revision 1

- PCI Express PIPE Endpoint Core does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging and is not needed for normal operation.

New Features v1.3 Revision 1

- Added 8.1i Service Pack 2 support.

Fixed Issues v1.3 Revision 1

- PME_TO_ACK message TLP routing field corrected.

- Corrected an unsolicited ERR_FATAL message TLP that was generated when fatal error reporting was enabled. An ERR_FATAL message was generated if received Ack DLLPs were discarded as a result of CRC error, and TLP Replay occurred as a result of Ack Timeout.

- Corrected an unsolicited ERR_NONFATAL message TLP that was generated. If nonfatal error reporting was enabled, ERR_NONFATAL message TLP was generated on receipt of Configuration Read Type0 TLP with Bus and Device number not equal to Bus, and Device number on a previously received Configuration Write Type0 TLP.

- Reads to Device Serial Number Extended Capability Register or any user PCI Express Extended Capability register (Byte Offsets 0x400 to 0xFFF) were returning the Device and Vendor ID or all 0s when using the pci_exp_1_lane_32b_ep and pci_exp_4_lane_32b_ep cores. This issue has been corrected.

- Corrected an issue that occurred when the CORE Generator GUI "Advanced Link Layer Settings" box labeled "Automatically calculate timer values" was unchecked, which caused the core to incorrectly allow a value of "0" to be driven into timeout counters.

Known Issues v1.3 Revision 1

- See (Xilinx Answer 23129) for information on the Advanced Link Layer Setting sections of the CORE Generator customization GUI.

- PCI Express PIPE Endpoint Core does not implement the "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging and is not needed for normal operation.

New Features v1.3

- Port changes.

- Removed SYS_CLK input port (the port existed but was not used in previous releases).

- Added CFG_TRN_PENDING_N input port. Allows you to signal when a transaction is pending.

- Support added for Spartan-3/-4 and Spartan-3E -5 device speed grades.

Known Issues v1.3

- See (Xilinx Answer 22679) regarding issues with the PME_TO_ACK message routing field.

- See (Xilinx Answer 22723) regarding information about reading PCI Express Extended Capability registers in the pci_exp_1_lane_32b_ep and pci_exp_1_lane_64b_ep cores.

- See (Xilinx Answer 22783) for issues regarding the "Automatically calculate timer values (Recommended)" option in Panel 7 of the CORE Generator customization GUI.

- PCI Express PIPE Endpoint Core does not implement "Loopback Slave" feature required by PCI Express Base Specification v1.1, section 4.2.6.10. PCI Express Endpoint cannot be put into "Loopback Slave" mode. This mode is primarily used for testing and debugging and is not needed for normal operation.

Revision History

09/22/2009 - Added reference to NXP data sheet.

AR# 22322
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article