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AR# 22331

LogiCORE XAUI v6.1 Core - Release Notes and Known Issues for the XAUI Core


This Answer Record contains the Release Notes for the LogiCORE XAUI v6.1 Core that was released in 8.1i IP Update #1 and includes the following: 


- New Features in v6.1 

- Bug Fixes in v6.1 

- Known Issues in v6.1  


For installation instructions and design tools requirements, see (Xilinx Answer 22155).


New Features in v6.1 


- Virtex-4 RocketIO clocking updated 

- Support added for ISE 8.1i 

- Support added for Cadence IUS (NC-Sim and associated compiler) 

- Example Design includes Calibration Block v1.2.1 for the Virtex-4 FX RocketIO (Tested in Hardware) 


Bug Fixes in v6.1 


- None 


Known Issues in v6.1 


1. The example design contains an incorrect period value for DCLK in the calibration block. For more information on this issue and details on how to work around it, see (Xilinx Answer 22662)


2. The XAUI Data Sheet in the lounge lists that Virtex-4 FX20 or larger as supported, but the data sheet in COREGen specifies that Virtex-4 FX60 is the only supported Virtex-4 device. For more information, see (Xilinx Answer 22951)


3. The example design currently uses the Virtex-4 v1.2.1 calibration block for CES2/3. To get the latest calibration block v1.2.2 for CES2/3 see (Xilinx Answer 22477). To migrate from the Virtex-4 v1.2.1 calibration block (CES2/3 requirement) to the v1.4.1 calibration block (CES4 requirement), install the patch provided below. For more information on the Virtex-4 calibration blocks, see (Xilinx Answer 22477)


4. Virtex-4 GT11 attributes are targeted for CES2/3. To update attributes for CES4, install the patch given below. 


5. Virtex-4 FX GT11 jitter errata causes a large amount of jitter on the serial line using a reference clock of 156.25 MHz. To avoid this issue, Xilinx recommends a 2x (312.5 MHz) reference clock. The patch below implements this clocking scheme. For more information, see (Xilinx Answer 23362) and the Virtex-4 FX errata. 


6. The example design for Virtex-4 has incorrect CHAN_BOND_LIMIT values on the GT11s. For more information on this issue and details on how to work around it, see (Xilinx Answer 23202)


7. Virtex-4 GT11 attribute TXCLK0_FORCE_PMACLK should be set to false. To update, install the patch below. 


8. Virtex-4 DCM in example design should be set for high frequency mode. To update, install the patch below. 


9. Virtex-4 example design should wait for 12000 clock cycles after TXLOCK is asserted by the MGT, before asserting TXSYNC. To update, install the patch below. 


10. The Virtex-4 GT11 attribute ALIGN_COMMA_WORD is incorrect. For more information on this issue and details on how to work around it, see (Xilinx Answer 23684)



To update to CES4 and resolve issues 1, 2, 3, 4, 5, 6, 7, 8, 9 and from the list of issues above, apply the following patch to the Xilinx ISE installation with the 8.1i Service Pack 3 and IP Update #1. A second revision has been made to the patch to update the reset logic to match the Virtex-4 RocketIO Users Guide v3.0: 



1. Install the patch by extracting the contents of the ".zip" or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure predefined in the archive.  



Determine the Xilinx installation directory by entering the following at the command prompt: 

echo %XILINX% 


UNIX or Linux 

Determine the Xilinx installation directory by entering the following: 

echo $XILINX 


NOTE: You might be required to have system administrator privileges to install the patch.  


2. After installing the patch, regenerate the XAUI Core from CORE Generator. The core and supporting files produced will contain the updates mentioned above.

AR# 22331
Date 05/19/2014
Status Archive
Type General Article
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