My Hardware in the Loop (HITL) Co-Sim design does not work when I have a DSP48 in my design. Why?
There is a known problem where MAP pulls registers into the DSP48, breaking the pipelining.
This seems to affect FIR filters built using DSP48 slices and various cores which use the DSP slice such as the FFT core. MAP/PAR is adding registers to my design.
For more information, please see (Xilinx Answer 22314).