This Release Note is for the SPI-3 (POS-PHY L3) Link Layer v4.1 Core released in 8.1i IP Update 1; it contains the following information:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 22155).
This core is automatically delivered with ISE8.2i DVD Release.
New Features in v4.1
- Support added for ISE 8.1i
- NC-Sim Support added
Bug Fixes in v4.1
Known Issues in 4.1
-(Xilinx Answer 22717) The example testbench may send packets beyond the maximum selected.
-(Xilinx Answer 22027) PAR displays: "INFO:Par:62 - Your design did not meet timing."
-(Xilinx Answer 22042) PAR places the clock pin and DCM on opposite sides of the chip, causing timing failures.
-(Xilinx Answer 22043) "ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed."
-(Xilinx Answer 22028) BitGen: "ERROR:PhysDesignRules:755 - IOB comp <TX_DTPA(16)> at location <AH34> is VCCO."
-(Xilinx Answer 22053) When I simulate a design example, data is sent to channels not used by the core.