AR# 22415

8.1i/7.1i Simulation, Virtex-4 - The UniSim BUFGCTRL VHDL model has 100 ps delay on output

Description

Keywords: ModelSim, NC-VHDL, discrepancy

The UniSim BUFGCTRL VHDL model has 100 ps delay on output, causing a discrepancy between the Verilog and VHDL model.

Solution

This issue is fixed in the latest 8.1i Service Pack, available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.1i Service Pack 1.

This is a problem in the simulation models.

There is also a patch available for this model at:
http://www.xilinx.com/txpatches/pub/swhelp/ise7_updates/cr221551.tar.gz

Instructions for patch:

Date: Nov 22nd, 2005

File Name: cr221551.tar.gz

Description: Patched BUFGCTRL and BUFR to remove the 100 ps delay as noted in CR 221551

Platform: ALL

Applicable Software version: 7.1i Service Pack 4.

Installation/Use:

Extract the archived file as shown below:

PC :

Use any unzip utility to unarchive this file.

Make a backup of the "simprims" directory in the XILINX installation directory, prior to extracting this file.

Extract these files to the XILINX installation directory.

Once the files have been extracted, re-run CompXLib to ensure that these are the files being used.

Unix / Linux:

Make a backup of the "simprims" directory under the "$XILINX" tree

Type the following:
>gunzip cr221551.tar.gz
>tar -C $XILINX -xvf cr221551.tar

Once the files have been extracted, re-run CompXLib to ensure that these are the files being used.

Testing:

Once this is complete, test out the design that failed to work. It should work correctly.
AR# 22415
Date 10/16/2008
Status Archive
Type General Article