If an HDL source is created using the New Source Wizard and it does not contain any ports, it will be associated with the wrong Design View and does not appear in the Synthesis/Implementation Source View.
Example: 1. Select New Source -> VHDL Module (or Verilog Module). 2. Enter a name for the module. 3. Continue through the New Source Wizard leaving default settings. After the VHDL Module is created, the Sources window appears to refresh, but the VHDL module is not listed in the hierarchy. 4. Change from Synthesis/Implementation to Behavioral Simulation, and the HDL module shows up there.
The new HDL source is being incorrectly associated to "Simulation Only".
This can be fixed with the following procedure: 1. Remove the new HDL source from the project by selecting it in the Behavioral Simulation view and pressing the Delete key. 2. Select Project -> Add Source... and select the HDL source file and then click Open. 3. In the Adding Source Files... window, change the file association from "Simulation Only" to "Synthesis/Imp + Simulation".
If any ports are added to the new HDL source during creating in the New Source Wizard, the ".vhd" file will be correctly added to the Synthesis/Implementation view in the Sources window.