When I use the IDELAY component in default mode in Virtex-4 LX100, I find the Tidid values are two different numbers in setup and hold path timing analysis. Since the IDELAY default value should be defined during chip fabrication, why do I see two different values in the timing report? Which one should be the real number for hardware implementation?
Usually, the IDELAY default value is defined in the speed file and should not show such a big discrepancy in setup/hold path analysis (9.701 and 4.993 ns).
This behavior is a result of a design difference between the Toshiba and UMC mask sets for the LX100. Thus, the legacy IDELAY can have a wide range of values. Since the speed files do not know which foundry a part came from (the speed files have to support both), the speed file has to set the maximum delay for setup path based on the largest possible delay, and the minimum delay for hold path based on the smallest possible delay.
This influences only the LX100 device.
Xilinx encourages the use of the FIX mode for tighter sample windows.
The other parts do not exhibit this wide spread in Tidid values between setup and hold for legacy delays.