We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22464

8.1i EDK - How can I reflect the addition or removal of I/Os in my EDK design after I have added XMP source in my ISE design?


I added an XMP file in my ISE project. When I click on "View HDL Instantiation Template", I can view the instantiation template for my processor system. Then, I return to EDK and add some I/Os in my processor system and regenerate the netlist in EDK. When I return to ISE and select "View HDL Instantiation Template" again, I do not see the I/Os that I added in my EDK design.


To solve this problem, follow these steps:

1. Once you modify your EDK design by adding or removing the external ports and before regenerating the netlist, select Tools -> Clean -> Hardware.

2. Select Tools -> Netlist.

3. In ISE, select "View HDL Instantiation Template" with "XMP source" selected in the "Sources for Project" window. You should see the I/O changes.

AR# 22464
Date 12/15/2012
Status Active
Type General Article