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AR# 22476

7.1i SimPrim, Timing Simulation - Fatal: (vsim-3420) Array lengths do not match Left is <width>. Right is <width>

Description

Keywords: VHDL, RAMB, SimPrim, -bp, MAP, pack, NetGen, ModelSim

Urgency: Standard

General Description:
When I run a timing simulation, I receive the following error when trying to load the design in ModelSim:

"# ** Fatal: (vsim-3420) Array lengths do not match. Left is <width>. Right is <width>."

Solution

This is a problem with the -bp switch in MAP. The correct INIT strings are not being passed when mapping unused slice logic to block RAMs.

To work around this issue, do not use the -bp switch with MAP.

This issue is fixed in ISE 8.1i.
AR# 22476
Date Created 09/04/2007
Last Updated 10/16/2008
Status Archive
Type General Article