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AR# 22477

Virtex-4 RocketIO - Calibration Block for CES2, CES3, and CES4 FX devices

Description

Keywords: MGT, PMA, PLL, lock

The Calibration Block is a design module delivered as Verilog and VHDL that connects to the GT11 RocketIO MGT found in the Virtex-4 FX family of FPGAs. The Calibration Block monitors the RX and TX lock signals and the MGT clocks generated within the MGT to ensure that correct PLL operation is established. The Block performs Dynamic Reconfiguration Port (DRP) operations upon user RX or TX PMA reset and during PLL initialization.

The Calibration Block also provides a solution for inactive transceivers. Inactive transceivers are instantiated and connected, but are not currently transmitting or receiving data. For more information on inactive transceiver behavior, see (Xilinx Answer 22471).

Solution

Three versions of the Calibration Block are available (see below). Working design examples are provided with the RocketIO Wizard; see (Xilinx Answer 22499). Use the version that corresponds to the FX device you are targeting.

NOTE: Calibration Block v1.2.1 was updated to v1.2.2 on May 19, 2006. If you are using v1.2.1, you must upgrade to v1.2.2.

CES2, CES2L, CES2R, CES3, CES3L, CES3R:
Use Calibration Block v1.1.1 or v1.2.2

CES2V2, CES2L2, CES2R2, CES3V2, CES3L2, CES3R2:
Use Calibration Block v1.2.2 only

CES4:
Use Calibration Block v1.4.1 only.
(For more details, see FAQs for v1.4.1 below.)

Each of the following download links prompt you to log in to your Xilinx.com account and accept a license agreement. After doing so, click the "Download Design File" link.

Calibration Block v1.1.1:
http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?iLanguageID=1&ipoid=24332297&category=-1210767&filename=mgt_cb_v1_1_1.zip&file=541

Calibration Block v1.2.2:
http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?iLanguageID=1&ipoid=24332297&category=-1210767&filename=mgt_cb_v1_2_2.zip&file=585

Calibration Block v1.4.1:
http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?iLanguageID=1&ipoid=24332297&category=-1210767&filename=mgt_cb_v1_4_1.zip&file=540

Known Issues

- The Signal Detect FSM in the Calibration Block can stall when RX_SIGNAL_DETECT is asynchronously asserted. When instantiating the Calibration Block in the design, the signal connecting to the RX_SIGNAL_DETECT input port has to be synchronized to DCLK (i.e., RX_SIGNAL_DETECT must be synchronous to DCLK).
- Figure 2 of the Calibration Block User Guide (labeled "Calibration Block with DCM and GT11 Primitive") shows the "refclk_p" and "refclk_n" ports connected directly to a DCM through a buffer. This connection is not correct, as the device clocking architecture does not allow a connection between the REFCLK input pads and the MGTCLK primitive. The connection to the DCM through a buffer should be moved instead to the output of the MGTCLK primitive (labeled "GT11CLK_MGT") in the figure.

FAQs for v1.1.1
(FAQs for v1.2.2 and v1.4.1 are included below.)

Q. What is the polarity of the RESET port on the Calibration Block?
A. The RESET is active High. It should be held High until a valid clock is input to the DCLK port. For example, if the DCLK is sourced from a DCM block, the RESET should be asserted until the DCM is locked.

Q. Do I have to use the Calibration Block v1.1.1 with Digital CDR?
A. Yes. The Calibration Block v1.1.1 is required when using Digital CDR mode; however, the DISABLE port must be tied HIGH.


FAQs for v1.2.2
(FAQs for v1.4.1 are included below.)

Q. Why was Calibration Block v1.2.1 upgraded to v1.2.2?
A: Please see (Xilinx Answer 23324).

Q. What Version of ISE and Synplify should be used with Calibration Block v1.2.2?
A. ISE 7.1i SP4 or greater and Synplify 8.2.1. (Synplify 8.2 should not be used.)

Q. How do I use the C_SIMULATION parameter?
A. Set this parameter to "1" when running simulation; this shortens the delays for quicker simulation runs. Lock signals will be asserted approximately 150 microseconds from the de-assertion of TX/RX PMARESET. Set C_simulation to "0" when building hardware.

Q. When synthesizing in Synplify, several warnings are issued concerning these synthesis attributes. Should I be concerned?
// synthesis attribute use_sync_reset of cal_block_v1_2_2 is yes
// synthesis attribute use_sync_set of cal_block_v1_2_2 is yes
// synthesis attribute use_clock_enable of cal_block_v1_2_2 is yes
// synthesis attribute use_dsp48 of cal_block_v1_2_2 is no
A. These attributes are present for and understood by XST only. You can safely ignore the Synplify warnings.

Q. How do I use the C_TXPOST_TAP_PD parameter?
A. For internal serial loopback, set this parameter to "FALSE". For normal operation or external cable loopback, set this parameter to "TRUE". Ensure that "FALSE" or "TRUE" is capitalized.

Q. How do I calculate the TX_FD_WIDTH and RX_FD_WIDTH parameters?
A. These parameters control the width of the TX_FD_MIN and RX_FD_MIN ports.
Example
TX_FD_WIDTH = Ceiling(Log2(TX_FD_MIN+1))
Ceiling( ) means to take the smallest whole number greater than or equal to the value inside the parentheses.

Q. What clock frequency should be used for DCLK?
A. The DCLK port must be driven by a free-running clock between 25 MHz and 50 MHz.

Q. What is the polarity of the RESET port on the Calibration Block?
A. The RESET is active High. It should be held High until a valid clock is input to the DCLK port. For example, if the DCLK is sourced from a DCM block, the RESET should be asserted until the DCM is locked.

Q. Are BUFGs required for GT_TXOUTCLK1 and GT_RXRECCLK2 clocks?
A. If these clocks do not drive other user logic, they can be connected through local routing. Alternatively, you can use regional clock buffers (BUFRs) to drive these clocks. For more information, refer to the Calibration Block User Guide.

FAQs for v1.4.1

Q. When should I use the Calibration Block v1.4.1?
A. Calibration Block v1.4.1 is intended for use with CES4 devices, and is necessary only for work-arounds 3 and 4 of Static Operating Behavior outlined in (Xilinx Answer 22471).

Q. Can I continue to use Calibration Block v1.2.2 in my CES4 device?
A. No. This configuration is not tested and is not supported by Xilinx.

Q. If my design already uses a previous version of the Calibration Block, how do I migrate to v1.4.1?
A. Wrappers are provided in order to help users migrate designs from Calibration Block v1.1.1 or v1.2.1 to v1.4.1. See the following documents that are delivered along with Calibration Block v1.4.1:
- migration_v111_v141.pdf
- migration_v121_v141.pdf

Q. What versions of ISE and Synplify are supported with Calibration Block v1.4.1?
A. ISE 8.1i SP1 or higher is required. The block has been tested with Synplify 8.2.1 and 8.4.0.

Q. What simulator is supported with Calibration Block v1.4.1?
A. The block has been simulated with MTI 6.0d.

Q. When synthesizing in Synplify, several warnings are issued concerning these synthesis attributes. Should I be concerned?
// synthesis attribute use_sync_reset of cal_block_v1_4_1 is yes
// synthesis attribute use_sync_set of cal_block_v1_4_1 is yes
// synthesis attribute use_clock_enable of cal_block_v1_4_1 is yes
// synthesis attribute use_dsp48 of cal_block_v1_4_1 is no
A. These attributes are present for and understood by XST only. The Synplify warnings can be safely ignored.

Q. How do I use the C_TXPOST_TAP_PD parameter?
A. For internal serial loopback, set this parameter to "FALSE". For normal operation or external loopback, set this parameter to "TRUE". Ensure that "FALSE" or "TRUE" is capitalized.

Q. How do I use the C_RXDIGRX parameter?
A. For Digital CDR mode, set this parameter to "TRUE". For Analog CDR mode, set this parameter to "FALSE". Ensure that "FALSE" or "TRUE" is capitalized.

Q. What clock frequency should I use for DCLK?
A. The DCLK port must be driven by a free-running clock between 25 MHz and 50 MHz.

Q. What polarity is the RESET signal?
A. The RESET signal is active High. It should be held High until a valid clock is input to the DCLK port. For example, if the DCLK is sourced from a DCM block, RESET should be asserted until the DCM is locked.

Q. How should I set the TX_SIGNAL_DETECT and RX_SIGNAL_DETECT?
A. User logic drives these two signals Low for inactive transceivers, and High for active transceivers.

Q. I have a design that worked with Calibration Block v1.1.1 or v1.2.1, but when I migrated to v1.4.1, the design stopped working. What is causing this problem?
A. The problem could be related to one of the following:
- Calibration Block v1.4.1 can be used only for CES4 devices.
- RXCMADJ attribute must be set to "01".
- Steps outlined in the migration documents must be followed.
- RESET of the Calibration Block must be held High until a valid clock is input to the DCLK port.
- Parameter C_MGT_ID must be set to "0" for MGT A and "1" for MGT B.
- Parameters C_TXPOST_TAP_PD and C_RXDIGRX must be set correctly for your application (see Q/A above).

If the design still does not work, contact Xilinx Technical Support for assistance:
http://www.xilinx.com/support/services/contact_info.htm
AR# 22477
Date Created 09/04/2007
Last Updated 05/15/2008
Status Active
Type General Article