What is the DDR-2 termination guideline for ML461?
Single-ended write only operations (add, ba, etc.) are terminated with a 50 Ohm parallel terminator to VTT. DQ lines are terminated with a 50 Ohm parallel terminator at both ends of the line to VTT. Diff DQS lines are terminated with a differential 100 Ohm terminator at the SDIMM side and use DIFF_SSTL18_II_DCI termination at the Xilinx side. Diff CLK does not have 100 Ohm termination on ML461 board. Instead, per Micron TN-47-01, it is replaced by a 5 pf capacitor(http://download.micron.com/pdf/technotes/ddr2/tn_47_01.pdf.See figure 9.). The reason is that DIMM already has differential termination implemented for CLK.