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AR# 22507

11.1 EDK - How do I modify the ISE generated testbench to perform an XPS simulation in an ISE environment?

Description

How do I modify the ISE generated testbench to perform an XPS simulation in an ISE environment?

Or, if I create a custom testbench, what additional information should be added to include the block RAM initialization and configuration contents?

Solution

Create the testbench in the ISE tool as follows:

  1. Select the Project pull-down menu > New Source...
  2. Select VHDL Test Bench.
  3. Fill in the testbench name in the data entry field.
  4. Click Next.
  5. Select the top level VHDL file (system_stub by default).
  6. Click Next, then Finish.

Modify the newly created testbench:

  1. Add a configuration design unit between the ENTITY and the ARCHITECTURE for the top level VHDL file (system_stub by default):
    :
    ENTITY system_stub_tb_vhd IS
    END system_stub_tb_vhd;
    configuration system_stub_conf of system_stub is
    for STRUCTURE
    for system_i : system
    use configuration work.system_conf;
    end for;
    end for;
    end system_stub_conf;
    ARCHITECTURE behavior OF system_stub_tb_vhd IS
    :
  2. Instantiate the system_stub_conf in the newly created testbench file instead of the top level VHDL file (system_stub by default):
    uut: configuration work.system_stub_conf PORT MAP(
    fpga_0_RS232_RX_pin => fpga_0_RS232_RX_pin,
    :
    :
  3. Because the instantiation of the configuration design unit used direct instantiation, a component declaration is not needed, so comment out the component declaration of the top level VHDL file (system_stub by default).

NOTE: Starting with 12.1, there is an automatic method to include the block RAM initialization that does not require the use of configuration statements.

AR# 22507
Date Created 01/07/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • EDK - 11.1