The known issues for "Post Layout Static Timing Analysis of Xilinx Platform for Programmable Systems FPGA Using PrimeTime" still apply through 6.1i release and newer.
The latest known issues for Virtex-II Pro are as follows:
- Any constraint that is translated into pin constraints will not be handled by create_sdc (e.g., NET TIG, THRU).
- create_sdc is not translating period constraints for DCM correctly.
- PTC.pt file results in errors while sourced.
- If you have a synchronous pin on source and destination register, then offset in constraint analysis for the pin on the destination register will not be correct.
- Create_sdc gives return code 1 for startup test case.
- For flip-flops, offset in constraints are not matching between trce and PrimeTime, since data path delay is incorrect for SDF.
- For block RAM/GT/GT10/MULT/PPC405, setup hold triplets have incorrect entries (it should be rel min, max, max, but looks like it has rel min, max, adj max) causing a mismatch.
Please use trce or Timing Analyzer for all your static timing analysis, or contact Synopsys PrimeTime for SDC translation support.