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AR# 22578

ML40x boards - CPLD reference design does not always configure FPGA upon power up


Keywords: ML40x, configuration, readme, known, issue

Urgency: Standard

General Description:
The CPLD reference design that is provided for the ML40x intermittently fails upon power up and does not successfully program the FPGA. The device always programs successfully after the Prog button is pulsed.


The cause of this problem has been identified and the updated files can be found at:


The CPLD should be reprogrammed using this new file.
AR# 22578
Date 10/01/2008
Status Archive
Type General Article
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