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AR# 22579

State Diagram Editor - What is the required syntax for a state transition condition?


What syntax is allowed for condition statements for transitioning from one state to another?


The StateDiagram Editor understands the following syntax:

ABEL syntax :

Equations (e.g. a#b&c)

Single values (e.g. my_sig or !my_sig)

Does NOT accept equality statements (e.g. a==1 or a==b)

VHDL syntax when VHDL is selected as the output language.

If the ABEL syntax is used, you can change the output HDL language, and the proper syntax for the condition is written to the HDL file.

Example: My condition is !sig_a.

If the ABEL is the language the condition is written as "!sig_a"

If the Verilog is the language the condition is written as "~sig_a"

If the VHDL is the language the condition is written as "sig_a='0'"

VHDL conditions do not translate to the other two languages.
AR# 22579
Date 07/26/2010
Status Archive
Type General Article
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