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AR# 22585

8.1i/7.1i Simulation - Do Xilinx libraries support the verilog-2001 ability to set the 'default_nettype = none?

Description

Keywords: UniSim, Verilog, compiler, directive, default_nettype, functional, Synopsys, VCS, NCverilog, MTI

Urgency: Standard

General Description:
Do Xilinx libraries support the verilog-2001 ability to set the 'default_nettype = none?

Solution

No. The Xilinx Libraries are not coded to ensure there is no implied nettype. This is an addition to the Verilog-2001 LRM that allows the ability to tell the simulator tool to force the default_nettype to none. When this is done, the Xilinx libraries will error out, as the libraries are coded without an explicit nettype.

This switch should be avoided in the simulator.

This issue will be fixed in ISE 9.1i.
AR# 22585
Date Created 09/04/2007
Last Updated 10/16/2008
Status Archive
Type General Article