PAR runs through placement successfully on my design, but fails immediately in the router with the following error message about unroutable nets. What causes this?
This design is unrouteable.
To evaluate the problem please use fpga_editor.
Net: XYZ/Mtc8kF/Mtc8kFRx/Mtc8kFRxHeaderChk/RegHec1/Eq_stage_cyo8 is unroutable.
Net: XYZ/Mtc8kF/Mtc8kFRx/Reg4hsCRamState/Eq_stage_cyo3 is unroutable.
Net: XYZ/Mtc8kFRx/Reg4hsCRamState/Eq_stage_cyo8 is unroutable.
Net: XYZ/Hdlc8kFTx/Hdlc8kFTxControl/RegWrEnb/Eq_stage_cyo8 is unroutable.
Net: XYZ/Mtc8kFRx/Mtc8kFRxHeaderChk/RegHec3/Eq_stage_cyo3 is unroutable.
Net: XYZ/TxContractor/Eq_stage_cyo48 is unroutable.
End of routing conflict report
This design is unrouteable. ROUTER WILL NOT CONTINUE!!
This problem can occur when the PAR placer encounters a carry chain with a mixture of SLICEM and SLICEL component types. SLICEM components contain LUT RAM. The PAR router incorrectly breaks the carry chain into SLICEM and SLICEL specific chains. Depending on the slice configurations (BX pin available for route-through?), the misaligned carry connection might be unroutable.
This problem is scheduled to be fixed in 8.1isp2 (Feb 2006). Meanwhile, this problem can be avoided by using the placement results generated by timing-driven mapping. To do this, enable the timing driven MAP options and then use PAR options that do not require a re-placement of the design. This occurs when a higher effort level is specified for PAR than was specified for MAP. For best QOR, use "-ol high" for both MAP and PAR.