We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 226

VHDL: Implementing the XC3000/XC4000 readback function.


How to implement the Readback function in VHDL ?


The following is an example instantiation of the readback
function in VHDL. This example assumes that the readback
clock is cclk.

entity readbk is
port(trig: in bit;
data, rip: out bit);
end readbk;

architecture inst of readbk is

component RDBK
port(trig: in bit;
data, rip: out bit);
end component;


U1: RDBK port map(trig, data, rip);

end inst;

AR# 226
Date 05/08/2002
Status Archive
Type General Article
Page Bookmarked