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AR# 22661

8.1i CORE Generator - Verilog simulation libraries of some cores are not available in ISE 8.1i


Keywords: FIFO_Generator_V2.2, C_SHIFT_RAM_V8.0, Vhdl, Verilog, Simulation Library

The following CORE Generator IP cores have simulation source files for VHDL , but do not have Verilog.

These simulation files were available in ISE 7.1i with IP update #3. Why are they not available in ISE 8.1i?


This is because IP Update #3 from ISE 7.1i is not included in the 8.1i installation. The ISE 7.1i IP Update #3 was finished and released after ISE 8.1i design tools had already been finalized, tested, and released to manufacturing for the creation of DVDs. Therefore, cores that were added with IP Update #3 for 7.1i are not available in ISE 8.1i. These cores and simulation files are contained in IP Update #1 for ISE 8.1i.

A Verilog behavioral model is no longer being generated for the Shift Ram core. The alternative is to generate a Verilog structural (i.e., unisim) model from CORE Generator. The unisim model will be a bit slower to simulate, but will be an exact model of the netlist. See (Xilinx Answer 22333).

AR# 22661
Date 03/04/2008
Status Archive
Type General Article
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